82C452 Asiliant Technologies, 82C452 Datasheet
82C452
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82C452 Summary of contents
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... 82C452 Super VGA Graphics Controller Data Sheet September 1991 Y ® ...
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Copyright Notice Copyright © 1990, Chips and Technologies, Inc. ALL RIGHTS RESERVED. This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce, transmit, transcribe, store in a retrieval system, or translate into any language or computer language, ...
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Chips and Technologies, Inc. 3050 Zanker Road San Jose, California 95134 Phone: 408-434-0600 Telex: 272929 CHIPS UR FAX: 408-434-6452 Publication No.: DS82 Stock No.: 010452-002 Revision No.: 2.1 ...
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... Standard part supports 65 MHz video clock rate (50 MHz version also available) Full complement of applications software drivers available from Chips and Technologies 82C452 Super 16 16 VGA Controller 15 (Optional) 32KB BIOS ROM(s) 82C452 System Diagram (1) 256Kx4 (1) 256Kx4 or (1) or (2) or (1) or (2) 64Kx4 64Kx4 4 DRAM(s) DRAM(s) 4 (1) 256Kx4 (1) 256Kx4 12 ...
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... Revision Date By 0.8 05/8/90 DH 1.0 05/18/90 VS 1.1 05/31/90 DP 1.2 06/19/90 DP 2.1 08/90 ST Revision 2.1 Revision History Comment Conversion to Chips Standard Data Sheet Format (CSDSF) Included Memory and Clock Interface Diagrams Updated Timings based on latest characterization data Edits (VS, DH, RR and GT ) Initial Release 2 Revision History Preliminary 82C452 ...
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... AC Electrical Specs - Clock Timing.......... 113 AC Electrical Specs - Reset Timing .......... 113 AC Electrical Specs - AD Bus Mux Timing . 113 AC Electrical Specs - EISA/ISA Timing .... 115 AC Electrical Specs - MCA Bus Timing..... 117 AC Electrical Specs - DRAM Timing ........ 120 AC Electrical Specs - Video Timing.......... 125 Mechanical Specifications........................ 126 3 Table of Contents Page Preliminary 82C452 ...
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... Video Timing ...................................... 125 PFP-144 Package Mechanical Dimensions..... 126 Revision 2.1 List of Figures and Tables Page Table 1 82C452 Pin Usage Summary.................... 8 Minimum Video Subsystem Chip Count ....... Register Summary - CGA/MDA/Hercules .... 16 Register Summary - EGA Mode................ 16 Register Summary - VGA Mode ............... 16 Register Summary - Indexed Registers........ 17 Register Summary - Extension Registers...... 18 93 Global Control (Setup) Registers ...
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... The DIP switch state is read into an internal CPU accessible register when the command strobe (IORD/ or CMD/) is low. MULTIPLE VGAs It is possible to support up to sixteen 82C452s in one system. number assigned to it through the above mentioned DIP switches. memory and I/O address space. However, only one 82C452 responds to CPU accesses at a time ...
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... FCIN0 and FCIN1 can be read by the CPU at bits 5 and 6 of the Input Status Register 0. GRAPHICS CURSOR The 82C452 supports a 32 pixel wide and 512 pixel high graphics cursor. The cursor can be placed anywhere on the screen at pixel resolution. The cursor can also be made transparent. The Hardware cursor frees up CPU from managing the cursor in a Windows-like environment ...
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... VIDEO SUBSYSTEM CHIP COUNT Using the 82C452, a complete VGA-compatible 16- bit video subsystem for motherboard applications can be built with 15 ICs, including display memory, as shown in the following bill of materials table: Qty Chip type 1 82C452 VGA Chip 1 BT475 or BT477 RAMDAC 2 74LS245 Transceiver 2 74LS244 Buffer ...
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... AA0 143 M1D0 144 Revision 2.1 82C452 Pinouts 82C452 Super VGA Note: Pin names shown indicate ISA bus connections Pin names in brackets [...] indicate MCA bus connections Pin names in parenthese (...) indicate alternate function 82C452 Pinouts 8 Pinouts 72 BHE/ (SW4) [MIO/] 71 AEN (SW6) [S1/] 70 MEMR/ ...
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... A23) when ADREN/ is low. This bit is read into bit 4 of the Internal Switch Register (XR01) when the Switch Register is accessed by the CPU and ADREN/ is high. Address latched internally. Defines the current memory address as a valid address for 82C452. Ignored for I/O cycles. In High Multiplexed upper address and auxiliary data bus ...
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... I/O registers are not accessible bus systems, this pin is connected to the bus refresh pin (low indicates a memory refresh cycle to which the 82C452 should not respond). In MCA systems, this pin is connected to the VGA DISABLE/ signal). When ADREN/ is high, this bit is read into bit 6 of Internal Switch Register (XR01) when the Switch Register is accessed by the CPU ...
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... Out Low Connected to the Write input of the Palette DAC (G176, BT471, or compatible). Asserted when the 82C452 is enabled and an I/O Write occurs to addresses 3C6-3C9h (or 83C6h-83C9h if enabled). Out Low Indicates access to ROM space in PC-Bus interface systems ...
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... PIN DESCRIPTIONS Pin # Pin Name 36 AA8 34 AA7 29 AA6 25 AA5 21 AA4 13 AA3 8 AA2 4 AA1 143 AA0 38 BA8 32 BA7 27 BA6 23 BA5 15 BA4 11 BA3 6 BA2 2 BA1 141 BA0 139 WE/ 20 RAS/ 17 RAS2/ 134 CAS0/ 135 CAS1/ 136 CAS2/ 137 CAS3/ 140 ERMEN/ (GPOUT0) Revision 2 ...
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... PIN DESCRIPTIONS Pin # Pin Name 33 M0D7 28 M0D6 24 M0D5 16 M0D4 12 M0D3 7 M0D2 3 M0D1 142 M0D0 35 M1D7 31 M1D6 26 M1D5 22 M1D4 14 M1D3 10 M1D2 5 M1D1 144 M1D0 132 M2D7 130 M2D6 128 M2D5 124 M2D4 122 M2D3 120 M2D2 118 M2D1 115 M2D0 ...
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... PIN DESCRIPTIONS Pin # Pin Name PCLK 96 BLANK/ (DE) 97 HSYNC 98 VSYNC 110 XHSYNC/ 111 XVSYNC/ 108 SENSE 84 CRSR1 (GPOUT3) Out 83 CRSR0 (GPOUT2) Out Revision 2.1 Type Active Description Out High 8-bit video pixel output ...
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... CLK0, CLK1, and CLK2 are 3 clock inputs. One of In High the three is selected as the input dotclock per Misc Out- In High put Register (3C2h) bits 2 and 3. In High Memory Clock. Used to generate display memory control signals. (internally divided 4). Maximum frequency 40 Mhz in 82C452. VCC -- Power VCC -- VCC -- VCC -- VCC -- ...
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... REGISTER SUMMARY - CGA, MDA, AND HERCULES MODES Register Register Name STAT Display Status CLPEN Clear Light Pen Flip Flop SLPEN Set Light Pen Flip Flop MODE CGA/MDA/Hercules Mode Control COLOR CGA Color Select CONFIG Hercules Configuration RX, R0-11 '6845' Registers XRX, XR0-7F ...
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... REGISTER SUMMARY - INDEXED REGISTERS (EGA / VGA) Register Register Name SRX Sequencer Index SR0 Reset SR1 Clocking Mode SR2 Plane Mask SR3 Character Map Select SR4 Memory Mode SR7 Reset Horizontal Character Counter CRX CRTC Index CR0 Horizontal Total CR1 ...
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... EXTENSION REGISTER SUMMARY: 00-2F Reg Register Name XRX Extension Index Register XR00 Chip Version XR01 DIP Switch XR02 CPU Interface XR03 ROM Interface XR04 Memory Mapping XR05 Sequencer Control XR06 DRAM Interface XR07 -reserved- XR08 General Purpose Output Select B XR09 ...
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... EXTENSION REGISTER SUMMARY: 30-5F Reg Register Name XR30 Graphics Cursor Start Address High 8 XR31 Graphics Cursor Start Address Low8 XR32 Graphics Cursor End Address XR33 Graphics Cursor X Position High XR34 Graphics Cursor X Position Low XR35 Graphics Cursor Y Position High XR36 ...
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... EXTENSION REGISTER SUMMARY: 60-7F Reg Register Name XR60 (Blink Rate Control) XR61 (Text Color Mapping Control) XR62 (Text Color Shift Parameter) XR63 (Graphics Color Mapping Control) XR64 (Alternate Vertical Total) XR65 (Alternate Overflow) XR66 (Alternate Vertical Sync Start) XR67 (Alternate Vertical Sync End) ...
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... Panning and Pixel Padding Registers control pixel attributes on screen. External color palette registers handle CPU reads and writes to I/O address range functions, video 3C6h-3C9h. external to the 82C452 in the external color palette. Inmos IMSG176 (Brooktree BT471/476) compatible registers are documented in this manual. 21 Registers Reducing 32-bits of ...
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... These are used for backwards compatibility. Note: The state of most of the Standard VGA Registers is undefined at reset. All registers specific to the 82C452 (Extension Registers) are summarized in the Extension Register Table. Revision 2.1 handle video ...
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... Global Control (Setup) Registers Register Mnemonic Register Name – Setup Control – Global Enable – Extension Enable – Global ID SETUP CONTROL REGISTER Write only at I/O Address 46E8h Reserved VGA Enable VGA Setup Reserved This register is used with the PC-Bus Interface only. ...
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... DIP switch to be compared against 82C452, 2 DIP switch to be compared against 82C452, 3 DIP switch to be compared against 82C452, 4 DIP switch to be compared against 5 Reserved (0) 6 Address for Extension Registers 0: Extension registers at ...
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... General Control & Status Registers Register Mnemonic Register Name ST00 Input Status 0 ST01 Input Status 1 FCR Feature Control MSR Miscellaneous Output INPUT STATUS REGISTER 0 (ST00) Read only at I/O Address at 3C2h Reserved Switch Sense FCIN0 FCIN1 CRT Interrupt Pending ...
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... CRT HSYNC Polarity. 0=pos, 1=neg 7 CRT VSYNC Polarity. 0=pos, 1=neg (Blank pin polarity can be controlled via the Video Interface Register) 26 REGISTER I/O Address Select RAM Enable Clock Select Reserved Page Select Hsync Polarity VSYNC Polarity CLK0 CLK1 CLK2 None Preliminary 82C452 ...
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... CGA / Hercules Registers Register Mnemonic Register Name MODE CGA/Hercules Mode COLOR CGA Color Select HCFG Hercules Configuration CGA / HERCULES MODE CONTROL REGISTER (MODE) Read/Write at I/O Address 3B8h/3D8h Hi-Res Text Graphics Mode Monochrome Video Enable Hi-Res Graphics (CGA only) ...
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... Pixel Value 0 0 Color per bits 0 7-6 Reserved (0) Color Color 28 CGA / Hercules Registers Enables intensified background colors Enables intensified colors 0-3 Don't care Color Set Color Set 0 1 Color per bits 0-3 Green Cyan Red Magenta Brown White Preliminary 82C452 ...
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... Hercules emulation mode or if the extension registers are enabled. It may be read back through XR14 D3 & D2 cleared by RESET. 0 Enable Graphics Mode 0: Lock the 82C452 in Hercules text mode. In this mode, the CPU has access only to memory address range B0000h-B7FFFh. 1: Permit entry to Hercules Graphics mode ...
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... This page was intentionally left Revision 2.1 blank 30 Preliminary 82C452 ...
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... Sequencer Index Reserved This register is cleared by RESET. 2-0 These bits contain a 3-bit Sequencer Index value used to access sequencer data registers at indices 0 through 7. 7-3 Reserved (0) Revision 2.1 82C452 Sequencer Registers Index SEQUENCER RESET REGISTER (SR00) Read/Write at I/O Address 3C5h Index 00h Group 1 Protection 7-2 ...
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... This bit determines 3-0 7-4 32 Sequencer Registers Color Plane Enable Reserved Color Plane Enable 0: Write protect corresponding color plane 1: Allow write to corresponding color plane In Odd/Even and Quad modes, these bits still control access to the corresponding color plane. Reserved (0) Preliminary 82C452 ...
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... Fifth 8K of Plane 2 5 Sixth 8K of Plane 2 6 Seventh 8K of Plane 2 7 Eighth 8K of Plane 2 where 'code' is: Character Generator Select A (bits when bit-3 of the the attribute byte is one. Character Generator Select B (bits when bit-3 of the attribute byte is zero. 33 Sequencer Registers Preliminary 82C452 ...
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... A write to any other sequencer register may then be used to start both counters with reasonable synchronization to an external event via software control. This is a standard VGA register which was not documented by IBM. 34 Sequencer Registers Don't Care Preliminary 82C452 ...
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... CRT Controller Registers Register Mnemonic Register Name CRX CRTC Index CR00 Horizontal Total CR01 Horizontal Display Enable End CR02 Horizontal Blank Start CR03 Horizontal Blank End CR04 Horizontal Sync Start CR05 Horizontal Sync End CR06 Vertical Total CR07 Overflow ...
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... This register is used for all VGA and EGA modes on CRTs also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 7-0 Number of Characters displayed per scan line - 1. 36 Horizontal Display Preliminary 82C452 ...
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... Enable signal is delayed to compensate for internal pipeline delays. 7 Light Pen Reg. Enable: Must be 1 for nor- mal operation; when this bit is 0, CRTC reg- isters CR10 and CR11 function as lightpen readback registers. 37 CRT Controller Registers H Blank End DE Skew Control Light Pen Reg. Enable Preliminary 82C452 ...
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... Horizontal Sync Delay. These bits specify the number of character clocks that the Horizontal Sync is delayed to compensate for internal pipeline delays. 7 Horizontal Blank End Bit 5. Sixth bit of the Horizontal Blank End Register (CR03). 38 Horizontal Sync End Horizontal Sync Delay H Blank End Bit 5 Preliminary 82C452 ...
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... V Total Bit End Bit 9 V Sync Start Bit 9 Vertical Total Bit 8 Vertical Display Enable End Bit 8 Vertical Sync Start Bit 8 Vertical Blank Start Bit 8 Line Compare Bit 8 Vertical Total Bit 9 Vertical Display Enable End Bit 9 Vertical Sync Start Bit 9 Preliminary 82C452 ...
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... The vertical parameters in the CRT Control- ler (even for a split screen) are not affected, only the CRTC row scan counter (bits 0-4 of this register) and display memory addressing screen refresh are affected. 40 Scan Lines Per Row V Blank Start Bit 9 Line Compare Bit 9 Double Scan Preliminary 82C452 ...
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... These bits define the number of character clocks that the cursor is delayed to compen- sate for internal pipeline delay. 7 Reserved (0) Note: If the Cursor Start Line is greater than the Cursor End Line, then no cursor is generated. 41 Cursor End Scan Line Cursor Delay Reserved Preliminary 82C452 ...
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... K byte boundaries respec- tively. Text Cursor Mem. Index (Lower 8 bits) Lower 8 bits of the memory address where the text cursor is active. In CGA/MDA/Her- cules modes, this register wraps around at 16, 32, and 64 K byte boundaries respec- tively. Preliminary 82C452 ...
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... XR15D6 to determine the protection for group 0 registers. This bit is cleared by RESET. 0: Enable writes to CR00-CR07 1: Disable writes to CR00-CR07 CR07 D4 (Line Compare bit-8) is not affected by this bit Sync End V Interrupt Clear V Interrupt Enable Select Refresh Type Protect CRTC (Group 0) Preliminary 82C452 ...
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... Frame Buffer Address is incre- mented See CR17 D3 for further details. Double word Mode. 0: Frame Buffer Address is byte or word address; 1: Frame Buffer Address is doubleword address. Used in conjunction with CR17 D6 to select the display memory addressing mode. Reserved (0) Preliminary 82C452 0: ...
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... End Vertical Blank. These are the 8 low order bits of the scan line count which speci- fies the end of Vertical Blank. The vertical blank width, W, is: Value in Start Blanking Register - bit value to be programmed in the register Blank End (Lower 8 bits) Preliminary 82C452 ...
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... Double Word Mode 1 1 Double Word Mode Display memory addresses are affected as shown in the table on the following page. Hardware Reset (This bit is cleared by RESET) 0: Force HSYNC and VSYNC to be inactive. No other registers or outputs affected. 1: Normal Operation. (continued on following page) Preliminary 82C452 ...
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... The display memory address counter then sequentially addresses the display memory starting at address 0. Each subsequent row address is generated by the addition of the Offset Register contents. This register is not affected by the double scanning bit (CR09 D7). Preliminary 82C452 ...
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... CPU because vertical display is not enabled. Reads from this register are not decoded and will return indeterminate data. This is a standard VGA register which was not documented by IBM. 48 Clear Vert Disp Ena FF Ignored Preliminary 82C452 ...
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... CR17 - CR18 - NOTE: All the registers at address 3Cx fall under group 1. Revision 2.1 Group 2 Group 3 Group Yes - - - - - - - - - - - Bit 4 - Yes Bits 0-4 - Yes - Yes - - - - - - - - - - - - Bits 4-5 - Yes - Yes - Yes - - - - - 0,1,3-7 - Yes 49 CRT Controller Registers Unprotected - - - - - - - - - - - - - - - - - - Bits 5 Yes - Yes - Yes - Yes Yes - 0-3 Yes - Yes - Bit Preliminary 82C452 ...
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... This page was intentionally left Revision 2.1 blank 50 Preliminary 82C452 ...
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... Graphics Controller Registers Register Mnemonic Register Name GRX Graphics Index GR00 Set/Reset GR01 Enable Set/Reset GR02 Color Compare GR03 Data Rotate GR04 Read Map Select GR05 Graphics mode GR06 Miscellaneous GR07 Color Don't Care GR08 Bit Mask GRAPHICS CONTROLLER ...
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... Color Don't Care register) causes a logical placed on the CPU data bus for the corre- sponding data bit, a mis-match returns a log- ical 0. 7-4 Reserved (0) 52 Color Compare (Plane 0) Color Compare (Plane 1) Color Compare (Plane 2) Color Compare (Plane 3) Reserved Preliminary 82C452 ...
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... Read Mode 0. In Odd/Even mode, bit-0 is ignored. In Quad mode, bits 0 and 1 are both ignored. The four memory maps are selected as fol- lows: Bit 1 Bit 7-2 Reserved (0) 53 Map Select 0 Map Select 1 Reserved Map Selected Plane 0 Plane 1 Plane 2 Plane 3 Preliminary 82C452 ...
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... Color Compare and Color Don't Care registers. The CPU reads a logical match occurs for each pixel and logical mis-match occurs. In 16-bit read cycles, this operation is repeated on the lower and upper bytes. Preliminary 82C452 ...
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... Shifted put Out to: M0D6 M0D7 Bit0 M1D6 M1D7 Bit1 M2D6 M2D7 Bit2 M3D6 M3D7 Bit3 M0D4 M0D6 Bit0 M0D5 M0D7 Bit1 M2D4 M2D6 Bit2 M2D5 M2D7 Bit3 M0D0 M0D4 Bit0 M0D1 M0D5 Bit1 M0D2 M0D6 Bit2 M0D3 M0D7 Bit3 Preliminary 82C452 ...
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... Color Compare register don't care during a comparison. 1: The corresponding bit of the Color Compare register is enabled for color comparison. This register is active in Read Mode 1 only. 7-4 Reserved (0) 56 Ignore Color Plane 0 Ignore Color Plane 1 Ignore Color Plane 2 Ignore Color Plane 3 Reserved Preliminary 82C452 ...
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... The bit mask applies to all four planes simul- taneously. 0: The corresponding bit in each of the four memory planes is written from the corresponding bit in the latches. 1: Unrestricted manipulation of the corre- sponding data bit in each of the four memory planes is permitted. Revision 2.1 Graphics Controller Registers 57 Preliminary 82C452 ...
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... This page was intentionally left Revision 2.1 Graphics Controller Registers blank 58 Preliminary 82C452 ...
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... Attribute Controller Register Mnemonic Register Name ARX Attribute Index (for 3C0/3C1h) AR00-AR0F Internal Color Palette Data AR10 Mode Control AR11 Overscan Color AR12 Color Plane Enable AR13 Horizontal Pixel Panning AR14 Pixel Pad DACMASK External Color Palette Pixel Mask ...
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... Video Output 5-4 Select 0: Video bits 4 and 5 are generated by the internal Attribute Controller color palette registers. 1: Video bits 4 and 5 are the same as bits 0 and 1 in the Pixel Pad register (AR14). 60 The Blink frequency is Preliminary 82C452 ...
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... The output color combinations available on the status bits are as follows: Bit 5 Bit 7-6 Reserved (0) 61 Color Plane 0 Enable Color Plane 1 Enable Color Plane 2 Enable Color Plane 3 Enable Display Status Select Reserved Status Register 1 Bit 5 Bit Preliminary 82C452 ...
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... Video bit-6 if not 256-color Video bit-7 if not 256-color Reserved These bits are output as video bits 5 and 4 when AR10 They are disabled in 256 color mode. These bits are output as video bits 7 and 6 in all modes except 256-color mode. Reserved (0) Preliminary 82C452 ...
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... To allow saving and restoring the state of the video subsystem, this register is required since the external color palette chip automatically increments its index register differently depending on whether the index is written at 3C7h or 3C8h. This register is physically located in the 82C452 chip (PALRD/ is not asserted for reads from this I/O address). 63 Palette State 0 ...
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... The Green 0 Blue 0 82C452 therefore saves the state of which port Green 1 Blue 1 (3C7h or 3C8h) was last written and returns that Green 2 Blue 2 information on reads from 3C7h (PALRD/ is only ...
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... Graphics Cursor Y Position Low XR37 Cursor Graphics Cursor Mode XR38 Cursor Graphics Cursor Mask XR39 Cursor Graphics Cursor Color 0 XR3A Cursor Graphics Cursor Color 1 Revision 2.1 82C452 Extension Registers Index 00h 01h 02h 03h 04h 05h 06h 0Eh 2Ah 7Fh 0Ah 0Bh ...
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... Read only at I/O Address 3B7h/3D7h Index 00h Version number 7-0 This register contains the version number for the 82C452. Values start at 11h and are incremented for every silicon step. current production silicon reads 14h in this register. Revision 2.1 DIP SWITCH REGISTER (XR01) ...
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... This bit affects . 67 Extension Registers ROM Enable Reserved ROM Decode Enable 0: ROM space decode enabled. On reset ROM decode enabled with EISA/ISA- Bus interface, disabled with MCA interface. ROMCS/ active (low) for CPU reads to C0000h-C7FFFh. 1: ROM space decode disabled. Reserved (0) Preliminary 82C452 ...
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... MByte of display memory (4 planes 256 k each using 256k x 4 devices). 11: Not Used. 2 CRT Wrap Around 0: 82C452 will wrap around CRT addresses at 64k boundary for VGA compatibility regardless of the amount of memory on the board. (Default on Reset). 1: 82C452 generates addresses for the entire memory on the board ...
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... RAS can be low. Time out is derived as follows: RAS Timeout = (196 +50N)/fmclk where N = number programmed in 6-5. 7 DRAM PAGE Cycle type 0: Normal Page mode 1: Fast Page Mode (Static Column) Note: The above register on power up will default to 01001010. Revision 2.1 69 Extension Registers Preliminary 82C452 ...
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... Select bit A for ERMEN/ pin 1 Select bit A for TRAP/ pin 2 Select bit A for CRSR0 pin 3 Select bit A for CRSR1 pin 7-4 Reserved (0) 70 Extension Registers Select A for ERMEN/ pin Select A for TRAP/ pin Select A for CRSR0 pin Select A for CRSR1 pin Reserved Preliminary 82C452 ...
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... Enable divide by 4 for CPU addresses. This allows the video memory to be accessed sequentially in mode 13. Also, all of the memory is available in mode 13 by setting this bit. 7-3 Reserved (0) 71 Preliminary 82C452 Extension Registers Memory Mapping Mode Single/Dual Map CPU Address Divide by 4 Reserved ...
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... In the case of Dual mapping this register controls the CPU window into the display memory based on the contents of GR6 as follows: GR6 High Map 0 0B0000-0Bffffh 1 0A8000-0Affffh 2 Don't care 3 Don't care 7-6 Reserved (0) 73 Extension Registers High Map Reserved Preliminary 82C452 ...
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... MCA-bus and PC-bus. XR14 D7=0 Interrupt State PC Bus Disabled 3-state Enabled, Inactive 3-state Enabled, Active 3-state Note: Bit 7 should be set to '1' to enable the CRT interrupt function in the PC BUS. 74 Extension Registers XR14 XR14 D7=0 D7=1 MCA Bus PC Bus 3-state 3-state 3-state Low Low High Preliminary 82C452 ...
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... Feature Control (3BA/3DAh) Revision 2.1 5 Write Protect Group 6. (I/O Addresses 3C6- 3C9h). The PALRD/ and PALWR/ output signals are disabled and the 82C452 DAC state register is write protected. 6 Write Protect Group 0. Protect for CRT Controller registers CR00- CR07 except CR07 D4. This bit is logically ORed with CR11 D7 ...
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... Trap occurred on access to I/O Address 3D8h or 3D9h. 5 Trap occurred on access to CRT Controller registers CR00 through CR0B and CR10 through CR18. 7-6 Reserved (0) For all bits access occurred 1: Access occurred 76 Extension Registers Trap occurred at: 3B4/3B5h 3B8/3BFh 3Cxh 3D4/3D5h 3D8/3D9h CR00-0B or CR10-18 Reserved Preliminary 82C452 ...
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... Read/Write at I/O Address 3B7h/3D7h Index 1Bh This register is used in CRT low resolution CGA modes, Hercules graphics modes. 7-0 Alternate Horizontal Total. See CR00 for description. 77 Extension Registers Alternate H Sync End Alternate H Sync Delay End H Blank bit 6 Alternate H Total Preliminary 82C452 ...
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... Graphics mode (720x348 line mode). Revision 2.1 BLANK ALTERNATE OFFSET (XR1E) Read/Write at I/O Address 3B7h/3D7h Index 1Eh This register is used in low resolution CGA modes and Hercules graphics modes. 7-0 Alternate Offset. See CR13 for description. 78 Extension Registers Alternate Display Buffer Width Preliminary 82C452 ...
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... This is the only register used in extended write mode 1. Software must write into this register to initialize the hardware. 79 Extension Registers Sliding Hold Sliding Hold Preliminary 82C452 ...
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... Set Horizontal Blank Force Level Horizontal Sync Force 0: Set Horizontal Sync Force Level Set Horizontal Sync Force Level to 1 7-6 Reserved (0) 80 Extension Registers V Display Enable Force V Blank Force V Sync Force H Display Force H Blank Force H Sync Force Reserved Preliminary 82C452 ...
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... Level Horizontal Blank Force 0: Set Horizontal Blank Force Level Set Horizontal Blank Force Level Horizontal Sync Force 0: Set Horizontal Sync Force Level Set Horizontal Sync Force Level to 1 7-6 Reserved (0) 80 Preliminary 82C452 Extension Registers V Display Enable Force ...
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... Vertical Counter Reset 0: Normal Operation 1: A strobe on XVSYNC will reset the Vertical counter Note: Bit 6 and 7 should be set to 0 for normal operation. 81 Extension Registers Reserved External HSYNC Polarity External HSYNC Enable External VSYNC Polarity External VSYNC Enable H Counter Reset V Counter Reset Preliminary 82C452 ...
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... Lower bits of delay loaded into the internal horizontal counter when external HSYNC triggers. The value loaded determines the delay from external HSYNC detect to start of the horizontal timing chain. 82 Extension Registers Delay Horizontal High Reserved LOW REGISTER Delay Horizontial Low Preliminary 82C452 ...
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... Index 2Fh 7-0 Lower bits of delay loaded into the internal Vertical counter when external VSYNC triggers. The value loaded determines the delay from external VSYNC detect to start of the Vertical timing chain. 83 Extension Registers Delay Vertical Low Preliminary 82C452 ...
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... Read/Write at I/O Address 3B7h/3D7h Index 33h 3-0 Horizontal Cursor Position. Upper bits of Graphics Cursor Horizontal pixel position 6-4 Reserved (0) 7 Cursor Position 0: Cursor position is positive 1: Cursor position is negative 84 Extension Registers Cursor End Address H Cursor Position Reserved Cursor Position Preliminary 82C452 ...
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... Graphics Cursor Vertical pixel position. 7-4 Reserved (0) Revision 2.1 GRAPHICS CURSOR POSITION Y-LOW REGISTER (XR36) Read/Write at I/O Address 3B7h/3D7h Index 36h 7-0 Cursor Position. Lower bits of Graphics The Cursor Vertical pixel position. Upper bits of 85 Extension Registers Cursor Position Preliminary 82C452 ...
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... Reserved (0) Revision 2.1 GRAPHICS CURSOR MASK (PLANE ENABLE) REGISTER (XR38) Read/Write at I/O Address 3B7h/3D7h Index 38h 7-0 Cursor Mask 0: No Graphics Cursor action on corre- sponding color plane 1: Enable Graphics Cursor on corre- sponding color plane 86 Extension Registers Cursor Mask Preliminary 82C452 ...
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... Cursor Color 0 7-0 Cursor Color 0. Color value 0 for cursor mode 1. Revision 2.1 GRAPHICS CURSOR COLOR 1 REGISTER (XR3A) Read/Write at I/O Address 3B7h/3D7h Index 3Ah 7-0 Cursor Color 1. Color value 1 for cursor mode 1. 87 Extension Registers Cursor Color 1 Preliminary 82C452 ...
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... Test Function Pins. These bits are used for internal testing of the chip. They should be 0 for normal operation. 6 BA8 Control bit 0: BA8 is the 9th memory address output. 1: BA8 is a test input 7 Reserved (0) 88 Extension Registers 3-state Control Test Function BA8 Control Reserved (0) pins PALRD/, WR46E8/, HSYNC, Preliminary 82C452 ...
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... Attribute Controller. All other I/O addresses (color palette, Miscellaneous Output and Status) are always treated as 8-bit ports; DS16/ (IOCS16/) is never asserted for these ports. When the 16-bit interface is chosen, the 82C452 will always assert DS16/ (MEMCS16/ or IOCS16/) after ROMCS/ AD0-7 RDLO/ ...
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... Address bus bits 8-15 are connected directly to results in CC the 82C452. The control and direction signals for the multiplexer are provided by the 82C452. Since the EISA/ISA bus supports only memory, the high address pin ADDHI is connected ...
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... ROM addresses. Like the IBM VGA add in card for the EISA/ISA bus, the 82C452 supports both a setup mode and an enable/disable mode. This is controlled by bits 3 and 4 of I/O port 46E8h. All hardware to implement this is included inside the 82C452 ...
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... Also, 16-bit accesses to display memory assume that the 82C452 controls the entire 0A0000-0Bffffh address space. This requires that the 82C452 be the only active video card in the system. The PTMC pin is strapped high to enable the EISA/ISA bus interface. The external 16-bit multiplexer can be implemented using two buffers (LS244s) for the address bus and two transceivers (LS245s) for the data bus ...
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... LOW ROM D0-D7 D0-D7 A0-A14 E OE/ ROM Ax Dx OE/ CS/ LS244 E D0-7 E DIR LS245 LATCH ROMCS Out Dx Qx Block Diagram – ROM Paging 93 Functional Description ADO-15 ADREN/ 82C452 AD1-AD14 A0 +5 ROMCS/ CS/ AD0-AD14 CS/ A0 BHE/ BHE/ BHE/ 82C452 ADREN/ RDLO/ AD0-7 WR46E8/ ROMCS/ Preliminary 82C452 ...
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... CPU INTERFACE - MCA BUS The 82C452 supports the MCA interface when the strap pin (PTMC) is pulled low. The 82C452 has a multiplexed address and data bus. To use a 16-bit CPU interface, an external 16-bit multiplexer is required. This multiplexer can be implemented using two buffers (LS244s) on the address bus and two transceivers (LS245s) on the data bus ...
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... DS16/ RDY CSFB/ VGAREQ/ Revision 2.1 AD0-7 RDLO/ RDHI/ AD8-15 ADREN/ 82C452 ADDHI A16-18 BHE/ MIO/ SETUP/ DISA/ CMD/ S0/ S1/ RESET VGAINT DS16/ RDY CSFB/ VGAREQ/ Block Diagram – 16-bit MCA Interface 95 Functional Description PALETTE DAC D0-7 XA0-1 (latched) A0-1 RD/ PALRD/ WR/ PALWR/ Preliminary 82C452 ...
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... DISA/ pin to be high, and B. The 82C452 should be put in setup mode (bit-5 of port 94h = 1 causing SETUP/ pin to go low); bit 0 of port xx2h = 1 then the 82C452 will be put back in normal mode (bit-5 of port 94h = 0) PC Bus Interface A. Bit-3 of port 46E8h must be 1, and B. The 82C452 should be put in setup mode (bit-4 of port 46e8h = 1) ...
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... ADDHI MIO/ DISA/ Revision 2.1 MULTIPLE VGAs It is possible to support up to sixteen 82C452s in one system. Each 82C452 must have a unique number assigned to it through the above mentioned DIP switches. All 82C452s occupy the same memory and I/O address space. responds to CPU accesses at a time. The currently ...
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... OE/ A0-7 RAS/ CAS/ WE/ OE/ PLANE 1 A0-7 RAS/ CAS/ WE/ OE/ Revision 2.1 The typical loading on the DRAM interface lines is: The 82C452 can support MByte of memory. The 82C452 supports early write cycles into the DRAMs. 82C452 CAS3/ AA0-7 BA0-7 M0D0-7 DA0-3 D0-3 DA4-7 D0-3 DB0-3 D0-3 DB4-7 D0-3 Block Diagram – DRAM Interface for 256 KBytes ...
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... Block Diagram – DRAM Interface for 512 KBytes 99 Functional Description A0-7 /RAS DC0-3 /CAS D0-3 /WE /OE A0-7 /RAS DC4-7 /CAS D0-3 /WE /OE A0-7 DD0-3 /RAS /CAS D0-3 /WE /OE A0-7 /RAS DD4-7 /CAS D0-3 /WE /OE A0-7 /RAS DC0-3 /CAS D0-3 /WE /OE A0-7 /RAS DC4-7 /CAS D0-3 /WE /OE A0-7 /RAS DD0-3 /CAS D0-3 /WE /OE A0-7 /RAS DD4-7 /CAS D0-3 /WE /OE Preliminary 82C452 ...
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... D0-3 /WE /OE A0-8 /RAS DB0-3 /CAS D0-3 /WE /OE PLANE 1 A0-8 /RAS DB4-7 /CAS D0-3 /WE /OE Block Diagram – DRAM Interface for 1 MByte 100 Functional Description A0-8 DC0-3 /RAS /CAS D0-3 /WE /OE PLANE 2 A0-8 DC4-7 /RAS /CAS D0-3 /WE /OE A0-8 DD0-3 /RAS /CAS D0-3 /WE /OE PLANE 3 A0-8 DD4-7 /RAS /CAS D0-3 /WE /OE Preliminary 82C452 ...
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... The 82C452 supports a high speed page mode DRAM interface. This along with the 16-bit data path and intelligent CPU arbitration can improve CPU performance times. The 82C452 supports 256 KB, 512 KB and display memory as follows: 8 Devices 64K ...
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... RD/ and WR/ signals for the external palette by decoding CPU I/O addresses 3C6 - 3C9h as valid palette addresses also possible to program the 82C452 to decode addresses 83C6 - 83C9h. This allows the use of a palette/DAC like a Brooktree® Bt471 which has additional overlay registers and therefore needs more addressability ...
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... Block Diagram – Brooktree Palette DAC (BT47x) PALETTE DAC '244 5V 4.7K SENSE Block Diagram – Monitor Type Detection 103 Functional Description PALETTE DAC D0-7 RS0-2 RD/ WR/ R ANALOG OVL0-1 G VIDEO OVL2-3 B V0-7 BLANK DCLK CLK LS04 +5V R ANALOG G VIDEO B 150 LM339 Ohm + VREF - 4. 330 ohms + - Preliminary 82C452 ...
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... Block Diagram – Ultra High Resolution Monochrome Video Interface Block Diagram – Super High Resolution (4 Color) Video Interface Revision 2.1 4 V0-3 D0-3 SHIFT REGISTER 82C452 DIVIDE by 4 CLK2 SHIFT REGISTER 4 V0-3 D0 82C452 Q CLK2 104 Functional Description DOTCLOCK DOTCLOCK D Preliminary 82C452 ...
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... CLOCK INTERFACE 82C452 has 3 display clock inputs and 1 memory clock input. MCLK can also be used as a display clock. For a minimum system configuration 82C452 can support display clocks. This configuration will support up to 640x480 256 color mode. With an external multiplexer six display clocks can be supported. This is shown in the typical clock interface figure ...
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... SEL 7474 CLKSEL0 QA SEL0 CLKSEL1 QB SEL1 SEL2 SEL3 DB DA Block Diagram – Clock Interface - Clock Chip 106 Functional Description MCLK CLK0 CLK1 CLK2 FCOUT0/ FCOUT1/ 40 MHz MCLK OUT CLK0 CLOCK CHIP 82C452 CLK1 CLK2 FCOUT0/ FCOUT1/ Preliminary 82C452 ...
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... GRAPHICS CURSOR The 82C452 supports a 32 pixel wide and 512 pixel high graphics cursor. The graphics cursor can be positioned anywhere on the screen at pixel resolution. It can be enlarged and can be horizontally doubled to occupy 64 pixels on the screen. (It can still be placed at single pixel resolution on the screen). The cursor supports transparency and can be any arbitrary shape within the outside box. The hardware cursor is based on the definition of the graphics pointer in Microsoft Windows™ ...
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... The carry over data can be read back through a register. This register can also be written in to initialize the hardware. SUD registers are located at XR20-XR24. FRAME INTERRUPTS The 82C452 Supports frame interrupts on variable number of frames 1 through 32, (on reset: every frame). This feature is controlled by XR2A. 108 Functional Description Similar to write mode 0 ...
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... B. Write protect the CRT controller or alternate registers using the Write Protect Register. C. Permit the applications software to write CRT or alternate registers particular display were in use. The 82C452 will operate standard I/O write took place but will not permit protected registers to be altered. ALTERNATE REGISTER SETS The 82C452 supplies two sets of Display Parameter Registers ...
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... COMPATIBILITY PROGRAMMING To enable backward compatibility, the chip is programmed as follows: VGA Mode A. Program the 82C452 exactly analogous to IBM's VGA. Disable the additional bits in the new registers. B. Select VGA mode (default). EGA Mode A. Program the 82C451/452 exactly analogous to IBM's VGA. Disable the additional bits in the new registers ...
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... The 82C452 will automatically respond to text, half graphics and full graphics modes as defined in the Mode Control Registers (3B8h and 3BFh). The regular CRT Offset Register is used in Hercules text mode. In Hercules graphics mode, the offset is defined in the Alternate Offset and Auxiliary Offset Registers ...
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... This page was intentionally left Revision 2.1 blank 112 Preliminary 82C452 ...
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... Electrical Specifications 82C452 ABSOLUTE MAXIMUM CONDITIONS Symbol Parameter P Power Dissipation D V Supply Voltage CC V Input Voltage I V Output Voltage O T Operating Temperature (Ambient Storage Temperature STG Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions described under Normal Operating Conditions ...
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... T Clock Rise / Fall RF Note 1: For a 65 MHz video clock, MCLK should be 40 MHz. CLKIN (CLK0, CLK1, CLK2) MCLK 82C452 AC TIMING CHARACTERISTICS - RESET TIMING Symbol Parameter tRST RESET Pulse Width Note 2: In CLKIN/2 mode tRST must be 128 Tc minimum. Revision 2.1 Notes 82C452-50 82C452 Note 1 ...
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... AC TIMING CHARACTERISTICS - AD BUS MULTIPLEXER TIMING Symbol Parameter T Strobe falling to ADREN/ rising dnh T Strobe rising to ADREN/ falling dnl T ADREN/ rising to RDLO/ and/or RDHI/ falling rdl T ADREN/ falling to RDLO/ and/or RDHI/ rising rdh T ADREN/ rising to write data valid dd Strobe (CMD/ for MCA; IORD/, ...
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... AC TIMING CHARACTERISTICS - EISA/ISA BUS TIMING Symbol Parameter T1 IORD/, IOWR/ Pulse Width T2 MEMR/, MEMW/ Pulse Width T3 Address setup to Read/Write T3a Address hold from Read/Write Signal T4 MEMR/, MEMW/ hold from RDY (Memory) T5 IOCS16/ Delay from valid address T6 I/O Read Data delay from IORD/ ...
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... Data (Read) Data (Write) Revision 2 EISA/ISA Bus I/O Cycle Timing EISA/ISA Bus Memory Cycle Timing 117 Electrical Specifications 7(max) T 7(min (max (min Preliminary 82C452 ...
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... AC TIMING CHARACTERISTICS - MCA BUS TIMING Symbol Parameter T16 Status hold from CMD/ T17 Status active from address valid T18 BHE/ Setup to CMD/ T19 BHE/ hold from CMD/ T19A Address hold from CMD/ T20 CMD/ active from Status T21 CMD/ from address valid ...
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... Data (Read) Data (Write) RDY T DS16/ T CSFB/ T VGAREQ/ Revision 2 19A HIGH MCA Bus I/O Cycle Timing 119 Electrical Specifications 27(max) T 27(min Preliminary 82C452 ...
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... CMD/ Data (Read) Data (Write) RDY T DS16/ CSFB/ T VGAREQ/ Revision 2 19A MCA Bus Memory Cycle Tim- ing 120 Electrical Specifications 27(max 27(min Preliminary 82C452 ...
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... AC TIMING CHARACTERISTICS - DRAM TIMING Symbol Parameter Trc Read/Write Cycle Time Tras RAS/ Pulse Width Tar Column Address Hold from RAS/ Trp RAS/ Precharge Tcrp CAS/ to RAS/ precharge Tcsh CAS/ Hold from RAS/ Trcd RAS/ to CAS/ delay Trsh RAS/ Hold from CAS/ ...
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... T ds Data Out High T cac T rac DRAM Read / Write Cycle Timing ras High T rah High High Impedance DRAM Refresh Cycle Timing 122 Electrical Specifications cas Row Address Column Address T wch T dh Data Row Address Preliminary 82C452 ...
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... SLOW PAGE MODE DRAM TIMINGS Symbol Parameter Tpc Page Mode Cycle time Trsh RAS hold from CAS Tcp CAS Precharge Tcas CAS Pulse Width Tcah Column Address hold from CAS Tcac Data Access time from CAS Tds Wrtie Data Setup to CAS ...
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... CP T CSH T CAH T T ASC ASC Column Column T WCH T WCS Write Data Write Data DRAM Page Mode Write Cycle Timing 124 Electrical Specifications RSH T CAS T CAH T T WCH WP T CWL T RWL T DH Preliminary 82C452 ASR Row ...
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... RAS CAS CSH T CAH T ASC Column Column T ASC T T RCH T RCS T CAC HIGH Z Read T RAC DRAM Page Mode Read Cycle Timing 125 Electrical Specifications RSH T CAS T CAH T T RCS RRH T RCH T CAC HIGH Z Read Preliminary 82C452 ASR Row ...
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... AC TIMING CHARACTERISTICS - VIDEO TIMING Symbol Parameter Tcdhl CLKIN Rise to PCLK Fall Delay Tcdlh CLKIN Fall to PCLK Rise Delay Thin HSYNC delay from PCLK falling edge Tvin VSYNC delay from PCLK falling edge Tblk BLANK/ delay from PCLK falling edge ...
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... Chips P/N & Country of Origin Vendor Mask Identifier Date Code & Fab Control Code Lead Length See Note 2 Note 1: Note 2: 82C452 Suggested PCB Pad Layout Pad Size = 2. 0.30 mm (0.100 in x 0.012 in) 'A' Spacing = 0.65 mm (0.0256 or 0.026 in) (see note) 'B' Spacing = 0.65 mm (0.0256 or 0.025 in) (see note) Note: Revision 2.1 144-Pin ...