M69030 Asiliant Technologies, M69030 Datasheet - Page 347

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Display Memory Bandwidth
The graphics controller’s ability to support high performance Super VGA modes can be limited by display
memory bandwidth as well as the maximum allowable DCLK frequency. The maximum pixel rate that a
given MCLK frequency can support depends on the following:
1)
2)
3)
4)
As an example, suppose MCLK is 83 MHz and the pixel depth is 16 bpp. Then the maximum supportable
pixel rate for CRT and TFT displays is 83 MHz x 70% x 8 ÷ 2 = 232.4 MHz (8 bytes per MCLK, 2 bytes per
pixel). Any video mode that uses a 232.4 MHz or lower DCLK can be supported by the 83 MHz MCLK. For
an STN-DD panel, the maximum supportable pixel rate in 16 bpp modes is 83 MHz x 70% x 8 ÷ 3 = 154
MHz (8 bytes per MCLK, 3 bytes accessed per pixel). 16 bpp video modes using a 75 MHz or lower DCLK
can be supported by the 83 MHz MCLK with an STN-DD panel.
`efmp

Pixel depth (number of bytes per pixel): 1 byte for 8 bpp, 2 bytes for 16 bpp, 3 bytes for 24 bpp.
Number of additional bytes accessed for STN-DD frame buffering, usually one byte per pixel
(independent of pixel depth in main display memory). This effect is discussed further in the next
section. It applies only to STN-DD panels, not to CRT or TFT displays.
Utilization efficiency. The percentage of peak memory bandwidth needed for RAS overhead (RAS-
CAS cycles rather than CAS-only cycles), DRAM refresh, and CPU access. Peak memory
bandwidth is the product of MCLK and the number of bytes accessed per MCLK (e.g., 664MB/sec
for 83MHz MCLK). The graphics controller needs at least 20% of this peak bandwidth for RAS
overhead (higher for STN-DD buffer accesses and CPU accesses due to shorter DRAM bursts).
Allow at least an additional 10% bandwidth buffer for CPU accesses and DRAM refresh. This leaves
70% of MCLK cycles available for display refresh (10% allowance for the CPU may be grossly
inadequate for demanding applications such as software MPEG playback).
Multimedia frame capture. This factor is not included in the example calculations. Except where
otherwise noted, the graphics controller mode support estimates do not include provision for frame
capture from the video input port.
69030 Databook
Clock Generation
Revision 1.3 11/24/99
B-7