M69030 Asiliant Technologies, M69030 Datasheet - Page 233

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

XRCF
read/write at I/O address 3D7h with index at I/O address 3D6h set to CFh
shared by both pipelines A and B
Note: The default values of some of the bits of this register are determined by the settings of some of the
strapping pins at reset.
7-4
3
2
1
0
`efmp
A
&
B

Reserved
Power Sequencing Reference Clock Select
Dot Clock Source
Memory Clock Source
Reserved
69030 Databook
7
Clock Configuration Register
These bits always return the value of 0 when read.
0: The clock used to time the steps of panel powerdown or powerup is the reference input
clock divided by 384. Presuming that the reference clock is the usual 14.31818MHz, the
frequency resulting from this division should be 37.5KHz. This is the default after reset.
1: The clock used to time the steps of panel powerdown or powerup is the 32KHz clock
provided as an input on one of the GPIO pins. This same clock is usually also used to
provide a time base for memory refreshes during standby mode.
0: An external clock source received through the DCLKIN pin is used to provide the dot
clock. All three of the synthesizers otherwise used to generate the three selectable dot
clocks are disabled.
1: The three synthesizers used to generate the three selectable dot clocks are enabled.
Note:
of pin CFG_4 during reset is also readable via bit 4 of the Configuration Pins 0 Register
(XR70). Bit 4 of XR70 is read-only, while this bit is writable, allowing the source of the dot
clock to be changed after reset.
0: An external clock source is used to provide the memory clock. The synthesizer
otherwise used to generate the memory clock is disabled. The graphics controller is
configured to receive this external clock source on either one of two pins depending on the
state of pin CFG_4 during reset. If CFG_4 was pulled low by an external pull-down resistor
during reset, then the graphics controller will be configured to receive the external clock on
the MCLKIN pin. If CFG_4 was allowed to be pulled high by the internal pull-up resistor
during reset, then the graphics controller is configured to receive the MCLK/DCLK from the
internal clock synthesizer.
1: The synthesizer used to generate memory clock is enabled.
Note:
of pin CFG_4 during reset is also readable via bit 4 of the Configuration Pins 0 Register
(XR70). Bit 4 of XR70 is read-only, while this bit is writable, allowing the source of the
memory clock to be changed after reset.
This bit always returns the value of 0 when read.
6
The default state of this bit reflects the state of pin CFG_4 during reset. The state
The default state of this bit reflects the state of pin CFG_4 during reset. The state
Reserved
(0000)
5
Extension Registers
4
Power Seq
Ref Clock
(0)
3
Dot Clock
Source
(x)
2
Mem Clk
Source
Revision 1.3 11/24/99
(x)
1
Reserved
(0)
0
14-53