M69030 Asiliant Technologies, M69030 Datasheet - Page 139

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

CR40
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 40h
shadowed for pipelines A and B
7
6-4
3-0
`efmp
A
B
Pipe A Strt
Pipe B Strt
Addr En
Addr En

Extended Mode Start Address Enable
Reserved
Start Address Bits 19-16
69030 Databook
(0)
(0)
7
Extended Start Address Register
This bit is used only in extended modes, where bit 0 of the I/O Control Register (XR09) is
set to 1, to signal the hardware to update the start address. In extended modes, the start
address is specified with a 20 bit value. These 20 bits, which are provided by the Start
Address Low Register (CR0D), the Start Address High Register (CR0C) and bits 3-0 of this
register, are double-buffered and synchronized to VSYNC to ensure that changes
occurring on the screen as a result of changes in the start address always have a smooth
or instantaneous appearance. To change the start address in extended modes, all three
registers must be set for the new value, and then this bit of this register must be set to 1.
Only if this is done, will the hardware update the start address on the next VSYNC. When
this update has been performed, the hardware will set bit 7 of this register back to 0.
Whenever this register is written to, these bits should be set to 0.
The start address is a 16-bit or a 20-bit value that specifies the memory address offset from
the beginning of the frame buffer at which the data to be shown in the active display area
begins.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the start
address is specified with a 16-bit value. The eight bits of the Start Address High Register
(CR0C) provide the eight most significant bits of this value, while the eight bits of the Start
Address Low Register (CR0D) provide the eight least significant bits.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the start
address is specified with a 20-bit value. The four most significant bits are provided by bits
3-0 of this register, bits 15 through 8 of this value are provided by the Start Address High
Register (CR0C), and the eight least significant bits are provided by the Start Address Low
Register (CR0D). Note that in extended modes, these 20 bits are double-buffered and
synchronized to VSYNC to ensure that changes occurring on the screen as a result of
changes in the start address always have a smooth or instantaneous appearance. To
change the start address in extended modes, all three registers must be set for the new
value, and then bit 7 of this register must be set to 1. Only if this is done, will the hardware
update the start address on the next VSYNC. When this update has been performed, the
hardware will set bit 7 of this register back to 0.
6
Reserved
Reserved
(000)
(000)
5
CRT Controller Registers
4
3
Pipeline A Start Address Bits 19-16
Pipeline B Start Address Bits 19-16
2
(0000)
(0000)
Revision 1.3 11/24/99
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