W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 26

no-image

W83627DHG

Manufacturer Part Number
W83627DHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W83627DHG

Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W83627DHG
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
W83627DHG
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Company:
Part Number:
W83627DHG
Quantity:
95
Company:
Part Number:
W83627DHG
Quantity:
5 000
Part Number:
W83627DHG-A
Manufacturer:
WINBOND-PBF
Quantity:
3
Part Number:
W83627DHG-A
Manufacturer:
WINBOND/PBF
Quantity:
8
Part Number:
W83627DHG-A
Manufacturer:
WINBOND/PBF
Quantity:
508
Part Number:
W83627DHG-A
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Company:
Part Number:
W83627DHG-A
Quantity:
1 200
Part Number:
W83627DHG-AC
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Part Number:
W83627DHG-C
Manufacturer:
Winbond
Quantity:
1 000
Part Number:
W83627DHG-P
Manufacturer:
Winbond
Quantity:
1 000
Part Number:
W83627DHG-P
Manufacturer:
IDT
Quantity:
165
Part Number:
W83627DHG-P
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Part Number:
W83627DHG-PT
Manufacturer:
NUVOTON
Quantity:
20 000
Part Number:
W83627DHG-PT
0
5.6
The SPI employs a master-slave model and typically has three signal lines: serial data input line (SI),
serial data output line (SO), and serial clock line (SCK). Different slaves are addressed on the bus by
chip select signals from the master. The data bits are first shifted in/out the most significant bit (MSB).
The data are often shifted simultaneously out from the output pin and into the input pin. Among the
parameters, only the communication lines and the clock edge are defined by the SPI. The others differ
from device to device.
SPI Operation
To initiate the data transfer between the W83627DHG and a slave device, SCE# must go low. This
synchronizes the slave device with the W83627DHG. Data can now be transferred between the
W83627DHG and the slave device in one of two modes: the data is sampled either on the rising or the
falling edge of the clock.
In a slave device, a logic low is received on the SCE# line and the clock input is at the SCK pin, which
synchronizes the slave with the W83627DHG. Data is then received serially at the SI pin. During a write
cycle, data is shifted out to the SO pin on clocks from the W83627DHG.
5.5
SYMBOL
GA20M
KBRST
MCLK
MDAT
KDAT
KCLK
GP27
GP26
GP25
GP24
Serial Peripheral Interface
KBC Interface
PIN
59
60
62
63
65
66
I/OD
I/OD
I/OD
I/OD
I/OD
I/OD
I/OD
I/OD
O
O
I/O
12
12
16ts
16ts
16ts
16ts
16t
16t
16t
16t
Gate A20 output. This pin is high after system reset. (KBC P21)
Keyboard reset. This pin is high after system reset. (KBC P20)
Keyboard Clock.
General-purpose I/O port 2 bit 7.
Keyboard Data.
General-purpose I/O port 2 bit 6.
PS2 Mouse Clock.
General-purpose I/O port 2 bit 5.
PS2 Mouse Data.
General-purpose I/O port 2 bit 4.
-14-
DESCRIPTION
Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4

Related parts for W83627DHG