W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 154

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status.
Bit 7, 6: These two bits are set to logical 1 when UFR, bit 0 = 1.
Bit 5, 4: These two bits are always logical 0.
Bit 3: In 16450 mode, this bit is logical 0. In 16550 mode, bits 3 and 2 are set to logical 1 when a
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
1
0
0
time-out interrupt is pending. See the table below.
this bit is set to logical 0.
0
1
1
1
0
0
ISR
0
1
0
0
1
0
0
1
0
0
0
0
Interrupt
priority
First
Second
Second
Third
Fourth
7
-
6
Interrupt Type
UART Receive
Status
RBR Data Ready
FIFO Data Timeout
TBR Empty
Handshake status
0
5
4
0
-
3
INTERRUPT SET AND FUNCTION
2
Interrupt Source
No Interrupt pending
1. OER = 1
3. NSER = 1
1. RBR data ready
2. FIFO interrupt active level
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
TBR empty
1. TCTS = 1
3. FERI = 1
-142-
1
reached
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
4. SBD = 1
2. TDSR = 1
2. PBER =1
4. TDCD = 1
Publication Release Date: Aug, 22, 2007
W83627DHG
Read USR
1. Read RBR
2. Read RBR until FIFO
data under active level
Read RBR
1. Write data into TBR
2. Read ISR (if priority is
Read HSR
Clear Interrupt
third)
-
Version 1.4