W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 182

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Logical Device A, CR[E6h], bits 2~1. The following table shows the definitions of Logical Device A,
CR[E6h] bits 3 ~1.
For example, if Logical Device A, CR[E6h] bit 2 is set to “0” and bits 2~1 are set to “10”, the range of t2
timing is from 396(300 + 96) mS to 596(500 + 96) mS.
* In UBE and UBF version, PWROK2 generation is the same as PWROK generation.
14.4.1 The Relation among PWROK/PWROK2, ATXPGD and FTPRST# - both for UBE and
PWROK and PWROK2 signals as well as ATXPGD and FTPRST# input signals are interrelated.
Once the FTPRST# signal changes from high to low then to high, the PWROK and PWROK2 signals
will have the same transition after 28mS ~ 39mS delay.
following figure and table.
PWROK/PWROK2
3VCC
FTPRST#
LOGICAL DEVICE A,
UBF Version Only
CR[E6H] BIT
2~1
3
PWROK_DEL (first stage) (VSB)
Set the delay time when rising from PWROK_LP to PWROK_ST.
0: 300 ~ 500 mS.
1: 200 ~ 300 mS.
PWROK_DEL (VSB)
Set the delay time when rising from PWROK_ST to PWROK.
00: No delay time.
10: 96 mS
Figure 14.7
t3
-170-
T
L
T
L
The relation and parameter are illustrated in the
DEFINITION
01: Delay 32 mS
11: Delay 250 mS
Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4