W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 218

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Continued
CR E6h. (Default 1Ch)
2~1
BIT READ / WRITE
BIT
7
6
5
4
3
0
1
0
Reserved.
R / W-Clear
Reserved.
READ / WRITE
R / W
R / W
R / W
R / W
R / W
R / W
ENMDAT => (VSB)
Three keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY,
CRE0[1]) define the combinations of the mouse wake-up events. Please
see the table in CRE0, bit 4 for the details.
CASEOPEN Clear Control. (VSB)
Write 1 to this bit to clear CASEOPEN status. This bit will not clear the status
itself. Please write 0 after an event is cleared. The function is the same as
Index 46h bit 7 of H/W Monitor part.
Power-loss Last State Flag. (VBAT)
0: ON
1: OFF.
PWROK_DEL (first stage) (VSB)
Set the delay time when rising from PWROK_LP to PWROK_ST.
0: 300 ~ 500 mS.
1: 200 ~ 300 mS.
PWROK_DEL (VSB)
Set the delay time when rising from PWROK_ST to PWROK.
00: No delay time.
10: 96 mS
PWROK_TRIG =>
Write 1 to re-trigger the PWROK signal from low to high.
ATXPGD signal to control PWROK and PWROK2 generation
0: Enable.
1: Disable.
* This bit is available both for UBE and UBF version
-206-
DESCRIPTION
01: Delay 32 mS
11: Delay 250 mS
DESCRIPTION
Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4