W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 189

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17. GENERAL PURPOSE I/O
The W83627DHG provides 40 input/output ports that can be individually configured to perform a simple
basic I/O function or alternative, pre-defined function. GPIO port 6 is configured through control
registers in Logical Device 7, and GPIO ports 2 ~ 5 in Logical Device 9. Users can configure each
individual port to be an input or output port by programming respective bit in selection register (0 =
output, 1 = input). Invert port value by setting inversion register (0 = non -inverse, 1 = inverse). Port
value is read / written through data register.
In addition, only GP30, GP31 and GP35 are designed to be able to assert PSOUT# or PME# signal to
wake up the system if any of them has any transitions. There are about 16mS debounced circuit inside
these 3 GPIOs and it can be disabled by programming respective bit (LD9, CR[FEh] bit 4~6). Users can
set what kind of event type, level or edge, and polarity, rising or falling, to perform the wake-up function.
The following table gives a more detailed register map on GP30, GP31 and GP35.
GP30
GP31
GP35
EVENTROUTE I
LDA,
CR[FEh]
bit4
LDA,
CR[FEh]
bit5
LDA,
CR[FEh]
bit6
0: DISABLE
1: ENABLE
(PSOUT#)
EVENTROUTE II
LDA,
CR[FEh]
bit0
LDA,
CR[FEh]
bit1
LDA,
CR[FEh]
bit2
0: DISABLE
1: ENABLE
(PME#)
DEBOUNCED
LD9,
CR[FEh]
bit4
LD9,
CR[FEh]
bit5
LD9,
CR[FEh]
bit6
1 : DISABLE
0 : ENABLE
EVENT
-177-
0 : EDGE
1: LEVEL
LD9,
CR[FEh]
bit0
LD9,
CR[FEh]
bit1
LD9,
CR[FEh]
bit2
EVENT
TYPE
Publication Release Date: Aug, 22, 2007
LD9,
CR[F2h]
bit0
LD9,
CR[F2h]
bit1
LD9,
CR[F2h]
bit5
1 : FALLING
0 : RISING
POLARITY
EVENT
W83627DHG
LD9,
CR[E7h]
bit0
LD9,
CR[E7h]
bit1
LD9,
CR[E7h]
bit5
STATUS
EVENT
Version 1.4