W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 145
W83627DHG
Manufacturer Part Number
W83627DHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheet
1.W83627DHG.pdf
(268 pages)
Specifications of W83627DHG
Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10.2.8 Digital Input Register (DI Register) (Read base address + 7)
The Digital Input Register is an 8-bit, read-only register used for diagnostic purposes. In PC/XT or
PC/AT mode, only bit 7 is checked by the BIOS. When the register is read, bit 7 shows the complement
of DSKCHG#
In PS/2 mode, the bit definitions are as follows:
DSKCHG (Bit 7):
This bit indicates the complement of the DSKCHG# input.
Bit 6-3: These bits are always a logic 1 during a read.
DRATE1 DRATE0 (Bit 2, 1):
These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR
Register) (Write base address + 4)) for how the settings correspond to individual data rates.
HIGHDENS# (Bit 0):
0
1
In PS/2 Model 30 mode, the bit definitions are as follows:
500 KB/S or 1 MB/S data rate (high-density FDD)
250 KB/S or 300 KB/S data rate
,
while the other bits remain in tri-state. The bit definitions are as follows:
7
x
6
x
5
x
7
4
1
6
x
3
1
5
x
x
2
1
4
Reserved for the hard disk controller
During a read of this register, these bits are in tri-stat
x
1
1
3
x
0
2
-133-
DSKCHG
1
0
HIGH DENS#
DRATE0
DRATE1
DSKCHG
Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4