W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 167

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3.10 ECR (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
Bit 7-5: Read/Write. These bits select the mode.
Bit 4: Read/Write (Valid only in ECP Mode)
Bit 3: Read/Write
000
001
010
011
100
101
110
111
1
0
1
0
Standard Parallel Port (SPP) mode. The FIFO is reset in this mode.
PS/2 Parallel Port mode. In addition to the functions of the SPP mode, this mode has
an extra trait: Direction is able to tri-state the data lines. Furthermore, reading the
data register returns the value on the data lines, not the value in the data register.
Parallel Port FIFO mode. This is the same as SPP mode except that bytes are
written or DMAed to the FIFO. FIFO data are automatically transmitted using the
standard parallel port protocol. This mode functions only when direction is 0.
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed
into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and
automatically transmitted to the peripheral using the ECP Protocol. When the
direction is 1 (reverse direction), bytes are moved from the ECP parallel port and
packed into bytes in the ecpDFifo.
EPP Mode. EPP mode is activated if the EPP mode is selected.
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data is not
transmitted on the parallel port.
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
Disables the interrupt generated on the asserting edge of nFault.
Enables the interrupt generated on the falling edge of nFault. This prevents
interrupts from being lost in the time between the read of the ECR and the write of
the ECR.
Enables DMA.
Disables DMA unconditionally.
7
6
5
4
-155-
3
2
empty
full
service Intr
dmaEn
nErrIntrEn
MODE
MODE
MODE
Publication Release Date: Aug, 22, 2007
1
0
W83627DHG
Version 1.4