W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 153

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 3: TDCD. This bit indicates that the DCD# pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI # pin has changed from low to high after HSR was read by
Bit 1: TDSR. This bit indicates that the DSR# pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS# pin has changed state after HSR was read by the CPU.
11.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
Bit 6, 7: These two bits are used to set the active level of the receiver FIFO interrupt. The active level is
Bit 4, 5: Reserved
Bit 3: When this bit is set to logical 1, DMA mode changes from mode 0 to mode 1 if UFR bit 0 = 1.
Bit 2: Setting this bit to logical 1 resets the TX FIFO counter logic to its initial state. This bit is
Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit is
Bit 0: This bit enables 16550 (FIFO) mode. This bit should be set to logical 1 before the other UFR bits
BIT 7
the CPU.
the number of bytes that must be in the receiver FIFO to generate an interrupt.
automatically cleared afterwards.
automatically cleared afterwards.
are programmed.
0
0
1
1
7
BIT 6
0
1
0
1
6
5
4
3
2
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
1
-141-
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Publication Release Date: Aug, 22, 2007
01
04
08
14
W83627DHG
Version 1.4