W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 123

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10. FLOPPY DISK CONTROLLER
10.1 FDC Functional Description
The floppy disk controller (FDC) of the W83627DHG integrates all of the logic required for floppy disk
control. The FDC implements a FIFO which provides better system performance in multi-master
systems, and the digital data separator supports data rates up to 2 M bits/sec.
The FDC includes the following blocks: Precompensation, Data Rate Selection, Digital Data Separator,
FIFO, and FDC Core. The rest of this section discusses these blocks through the following topics: FIFO,
Data Separator, Write Precompensation, Perpendicular Recording mode, FDC core, FDC commands,
and FDC registers.
10.1.1 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM
(Request for Master) and DIO (Data Input/Output) bits in the Main Status Register.
The FIFO is defaulted to disabled mode after any form of reset, which maintains PC/AT hardware
compatibility. The default values can be changed through the configure command. The advantage of
the FIFO is that it lets the system have a larger DMA latency without causing disk errors. The following
tables give several examples of the delays with the FIFO. The data are based upon the following
formula:
At the start of a command, the FIFO is always disabled, and command parameters must be sent based
upon the RQM and DIO bit settings in the Main Status Register. When the FDC enters the command
execution phase, it clears the FIFO off any data to ensure that invalid data are not transferred.
An overrun or underrun terminates the current command and data transfer. Disk writes complete the
current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the
remaining data so that the result phase may be entered.
DMA transfers are enabled by the specify command and are initiated by the FDC when the LDRQ pin is
activated during a data transfer command.
FIFO THRESHOLD
FIFO THRESHOLD
15 Byte
15 Byte
2 Byte
8 Byte
1 Byte
2 Byte
8 Byte
1 Byte
DELAY = THRESHOLD # x (1 / DATA RATE) * 8 - 1.5 μs
2 x 16 μs - 1.5 μs = 30.5 μs
8 x 16 μs - 1.5 μs = 6.5 μs
15 x 16 μs - 1.5 μs = 238.5 μs
1 x 8 μs - 1.5 μs = 6.5 μs
2 x 8 μs - 1.5 μs = 14.5 μs
8 x 8 μs - 1.5 μs = 62.5 μs
15 x 8 μs - 1.5 μs = 118.5 μs
1 x 16μs - 1.5 μs = 14.5 μs
MAXIMUM DELAY UNTIL SERVICING AT 500K BPS
MAXIMUM DELAY UNTIL SERVICING AT 1M BPS
Data Rate
Data Rate
-111-
Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4