W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 21

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2
5.1
LFRAME#
LRESET#
SYMBOL
LAD[3:0]
SERIRQ
PCICLK
LDRQ#
DRVDEN0
IOCLK
PME#
SYMBOL
TRAK0#
INDEX#
STEP#
MOA#
DSA#
DIR#
WD#
WE#
FDC Interface
LPC Interface
24-27
PIN
18
86
21
22
23
29
30
PIN
10
11
13
1
3
4
6
8
9
OD
OD
OD
OD
OD
OD
OD
I/OD
IN
IN
OD
I/O
I/O
IN
O
IN
IN
IN
cs
cs
24
24
24
24
24
24
24
I/O
12p3
tsp3
12tp3
tsp3
tsp3
tp3
12p3
12tp3
Drive Density Select bit 0.
This Schmitt-trigger input from the disk drive is active-low when the
head is positioned over the beginning of a track marked by an index
hole. This input pin needs to connect a pulled-up 1-KΩ resistor to 5V for
Floppy Drive compatibility.
Motor A On. When set to 0, this pin activates disk drive A. This is an
open-drain output.
Drive Select A. When set to 0, this pin activates disk drive A. This is an
open-drain output.
Direction of the head step motor. An open-drain output.
Logic 1 = outward motion
Logic 0 = inward motion
Step output pulses.
pulse to move the head to another track.
Write data. This logic-low open-drain writes pre-compensation serial
data to the selected FDD. An open-drain output.
Write enable. An open-drain output.
Track 0. This Schmitt-trigger input from the disk drive is active-low
when the head is positioned over the outermost track. This input pin
needs to connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive
compatibility.
System clock input, either 24MHz or 48MHz. The actual frequency
must be specified in the register. The default value is 48MHz.
Generated PME event.
PCI-clock 33-MHz input.
Encoded DMA Request signal.
Serialized IRQ input / output.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
Indicates the start of a new cycle or the termination of a broken
cycle.
Reset signal. It can be connected to the PCIRST# signal on the
host.
-9-
This active-low open-drain output produces a
DESCRIPTION
DESCRIPTION
Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4