DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 87

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If the buffer empties, then a full frame of data will be repeated at RSERO and the TR.SR5.0 and TR.SR5.1 bits will
be set to a one. If the buffer fills, then a full frame of data will be deleted and the TR.SR5.0 and TR.SR5.2 bits will
be set to a one.
10.12.2 Transmit Side
See the TR.IOCR1 and TR.IOCR2 registers for information on clock and I/O configurations. The operation of the
transmit elastic store is very similar to the receive side. If the transmit-side elastic store is enabled a 1.544MHz or
2.048MHz clock can be applied to the TSYSCLK input. For higher-rate system clock applications, see the
Interleaved PCM Bus Operation section. Controlled slips in the transmit elastic store are reported in the TR.SR5.3
bit and the direction of the slip is reported in the TR.SR5.4 and TR.SR5.5 bits.
10.12.2.1 T1 Mode
If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSERI will be ignored
every fourth channel. Hence, channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) will
be ignored. The user can supply frame or multiframe sync pulse to the TSSYNC input. Also, in 2.048MHz
applications, the TCHBLK output will be forced high during the channels ignored by the framer.
10.12.2.2 E1 Mode
A 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. The user must supply a frame-sync pulse
or a multiframe-sync pulse to the TSSYNC input.
10.12.3 Elastic Stores Initialization
There are two elastic-store initializations that can be used to improve performance in certain applications: elastic
store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write
pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLKT,
respectively). See
Table 10-11. Elastic Store Delay After Initialization
10.12.3.1 Minimum-Delay Mode
When minimum delay mode is enabled the elastic stores will be forced to a maximum depth of 32 bits instead of
the normal two-frame depth. TR.ESCR.5 and TR.ESCR.1 enable the transmit and receive elastic store minimum-
delay modes. This feature is useful primarily in applications that interface T1 to a 2.048MHz bus without adding the
latency that would be associated with using the elastic store in full buffer mode. Certain restrictions apply when
minimum delay mode is used. Minimum-delay mode can only be used when the elastic store’s system clock is
locked to its network clock (e.g., RCLK locked to RSYSCLK for the receive side and TCLKT locked to TSYSCLK
for the transmit side). RSYNC must be configured as an output. In E1 operation TSYNC must be configured as an
input when transmit minimum delay mode is enabled. In T1 operation TSYNC can be configured as an input or
output when transmit minimum delay mode is enabled. In a typical application RSYSCLK and TSYSCLK are
locked to RCLK, and RSYNC (frame output mode) is connected to TSSYNC (frame input mode). All of the slip
contention logic in the framer is disabled (since slips cannot occur). On power-up, after the RSYSCLK and
TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bits (TR.ESCR.2
and TR.ESCR.6) should be toggled from a zero to a one to ensure proper operation.
Receive Elastic Store Reset
Transmit Elastic Store Reset
Receive Elastic Store Align
Transmit Elastic Store Align
INITIALIZATION
Table 10-11.
for details.
REGISTER BIT
TR.ESCR.2
TR.ESCR.6
TR.ESCR.3
TR.ESCR.7
8 Clocks < Delay < 1 Frame
1 Frame < Delay < 2 Frames
½ Frame < Delay < 1 ½ Frames
½ Frame < Delay < 1 ½ Frames
87 of 335
DELAY