DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 151

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.5.4 X.86 Registers
X.86 transmit and common registers are used to control the operation of the X.86 encoder and decoder.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: X.86 Encoding Decoding (X86ED). If this bit is set to 1, X.86 encoding and decoding is enabled for the
Transmit and Receive paths. The MAC Frame is encapsulated in the X.86 Frame for Transmit and the X.86
headers are checked for in the received data. If X.86 functionality is selected, the X.86 receiver byte boundary is
provided by the RSYNC signal and the device provides the transmit byte synchronization TSYNC. No HDLC
encapsulation is performed.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: X86 Transmit Receive Address (X86TRA7 to X86TRA0). This is the address field for the X.86
transmitter and for the receiver. The register default value is 0x04.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: X86 Transmit Receive Control (X86TRC7 to X86TRC0). This is the control field for the X.86
transmitter and expected value for the receiver. The register is reset to 0x03
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: X86 Transmit Receive Address (TRSAPIH7 to TRSAPIH0). This is the address field for the X.86
transmitter and expected for the receiver. The register is reset to 0xfe.
X86TRA7
X86TRC7
TRSAPIH7
—
7
0
7
0
7
0
7
1
X86TRC6
X86TRA6
TRSAPIH6
—
6
0
6
0
6
0
6
1
LI.TX86EDE
X.86 Encoding Decoding Enable
0D8h
LI.TRX86A
Transmit Receive X.86 Address
0D9h
LI.TRX8C
Transmit Receive X.86 Control
0DAh
LI.TRX86SAPIH
Transmit Receive X.86 SAPIH
0DBh
X86TRC5
X86TRA5
TRSAPIH5
—
5
0
5
0
5
0
5
1
X86TRA4
X86TRC4
TRSAPIH4
151 of 335
—
0
0
0
1
4
4
4
4
X86TRC3
X86TRA3
TRSAPIH3
—
3
0
3
0
3
0
3
1
X86TRA2
X86TRC2
TRSAPIH2
—
2
0
2
1
2
0
2
1
X86TRC1
X86TRA1
TRSAPIH1
—
1
0
1
0
1
1
1
1
X86TRC0
X86TRA0
TRSAPIH0
X86ED
0
0
0
0
0
1
0
0