DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 68

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10 INTEGRATED T1/E1/J1 TRANSCEIVERS
10.1 T1/E1/J1 Transceiver Clocks
The device contains an on-chip clock synthesizer that generates a user-selectable clock referenced to the
recovered receive clock (RCLK). The synthesizer uses a phase-locked loop to generate low-jitter clocks. Common
applications include generation of port and backplane system clocks.
Figure 10-1
the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can
be placed in the receive or transmit path, two are shown for simplification and clarity.
Figure 10-1. Transceiver Clock Structure
The TCLKT MUX is dependent on the state of the TCSS0 and TCSS1 bits in the TR.CCR1 register and the state of
the TCLKT pin.
RXCLK
TXCLK
TO
LIU
shows the clock map of the transceivers. The routing for the transmit and receive clocks are shown for
MCLKS = 0
RCL = 1
RCL = 0
2.048 TO 1.544
SYNTHESIZER
PRE-SCALER
MCLK
LOCAL
LOOPBACK
LLB = 0
LLB = 1
MCLKS = 1
TR.LIC4.MPS0
TR.LIC4.MPS1
TR.LIC2.3
JITTER ATTENUATOR
SEE TR.LIC1
REGISTER
JAS = 0
OR
DJA = 1
JAS = 1
AND
DJA = 0
LTCA
LTCA
JAS = 0
AND
DJA = 0
JAS = 1
OR
DJA = 1
REMOTE
LOOPBACK
RLB = 1
RLB = 0
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DJA = 1
DJA = 0
FRAMER
LOOPBACK
FLB = 0
FLB = 1
TRANSMIT
FORMATTER
RECEIVE
FRAMER
8 x PLL
PAYLOAD
LOOPBACK
(SEE NOTES)
PLB = 1
PLB = 0
A
B
BPCLK
SYNTH
C
TCLKT
MUX
TSYSCLK
8XCLK
BPCLK
RCLKO
TCLKT