DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 142

IC TXRX ETHERNET MAP 400-BGA

DS33R41+

Manufacturer Part Number
DS33R41+
Description
IC TXRX ETHERNET MAP 400-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS33R41+

Number Of Drivers/receivers
4/4
Protocol
T1/E1/J1
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Register Name:
Register Description
Register Address:
Bits 7 to 0: SDRAM Refresh Time Control (SREFT7 to SREFT0). These 8 bits are used to control the SDRAM
refresh frequency. The refresh rate will be equal to this register value x 8 x 100MHz.
Note: This register has a non-zero default value. This should be taken into consideration when initializing
the device.
Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to write
the new values to the SDRAM.
Bit #
Name
Default
SREFT7
7
0
SREFT6
6
1
GL.SDRFTC
Global SDRAM Refresh Time Control
3Dh
SREFT5
5
0
142 of 335
SREFT4
4
0
SREFT3
3
0
SREFT2
2
1
SREFT1
1
1
SREFT0
0
0

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