DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 49

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
9.9 Connections and Queues
The multi-port devices in this product family provide bi-directional cross-connections between the multiple Ethernet
ports and Serial ports when operating in software mode. A single connection is preserved in this single-port device
to provide software compatibility with multi-port devices. The connection will have an associated transmit and
receive queue. Note that the terms “Transmit Queue” and “Receive Queue” are with respect to the Ethernet
Interface. The Receive queue is for data arriving from Ethernet interface to be transmitted to the WAN interface.
The Transmit queue is for data arriving from the WAN to be transmitted to the Ethernet interface. Hence the
transmit and receive direction terminology is the same as is used for the Ethernet MAC port.
The user can define the connection and the size of the transmit and receive queues. The size is adjustable in units
of 32(by 2048 byte) packets. The external SDRAM can hold up to 8192 packets of data. The user must ensure that
all the connection queues do no exceed this limit. The user also must ensure that the transmit and receive queues
do not overlap each other. Unidirectional connections are not supported.
When the user changes the queue sizes, the connection must be torn down and re-established. When a
connection is disconnected all transmit and receive queues associated with the connection are flushed and a “1’ is
sourced towards the Serial transmit and the HDLC receiver. The clocks to the HDLC are sourced a “0.”
The user can also program High and Low watermarks. If the queue size grows past the High watermark, an
interrupt is generated if enabled. The registers of relevance are described in
Table
9-5. The
AR.TQSC1
size
provides the size of the transmit queue for the connection. The High Watermark will set a latched status bit. The
latched status bit will clear when the register is read. The status bit is indicated by LI.TQCTLS.TQHTS. Interrupts
can be enabled on the latched bit events by LI.TQTIE. A latched status bit (LI.TQCTLS.TQLTS) is also set when
the queue crosses a low watermark.
The Receive Queue functions in a similar manner. Note that the user must ensure that sizes and watermarks are
set in accordance with the configuration speed of the Ethernet and Serial interfaces. The device does not provide
error indication if the user creates a connection and queue that overwrites data for another connection queue. The
user must take care in setting the queue sizes and watermarks. The registers of relevance are AR.RQSC1and
SU.QCRLS. Queue size should never be set to 0.
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