DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 333
DS33R41+
Manufacturer Part Number
DS33R41+
Description
IC TXRX ETHERNET MAP 400-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS33R41.pdf
(335 pages)
Specifications of DS33R41+
Number Of Drivers/receivers
4/4
Protocol
T1/E1/J1
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.6 JTAG Functional Timing
This functional timing for the JTAG circuits shows:
Figure 15-3. JTAG Functional Timing
(STATE)
JTRST
Output
JTCLK
(INST)
JTDO
JTMS
JTDI
•
•
•
•
•
Pin
The JTAG controller starting from reset state.
Shifting out the first 4 LSB bits of the IDCODE.
Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern.
Shifting the TDI pin to the TDO pin through the bypass shift register.
An asynchronous reset occurs while shifting.
Reset
X
Run Test
Idle
Select DR
Scan
Capture
DR
IDCODE
Shift
DR
X
Exit1
DR
Update
DR
333 of 335
Output pin level change if in "EXTEST" instruction mode
Select DR
Scan
Select IR
Scan
Capture
IR
Shift IR
X
Exit1
IR
Update
IR
X
Select DR
Scan
Capture
DR
BYPASS
Shift
DR
X
Logic Idle
IDCODE
X
Test
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