CY7C68014A-56BAXC Cypress Semiconductor Corp, CY7C68014A-56BAXC Datasheet - Page 53

• Manufacturer Part Number: CY7C68014A-56BAXC
• Description: IC MCU USB PERIPH HI SPD 56VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68014A-56BAXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• Core Size: 16bit
• No. Of I/o's: 24
• Program Memory Size: 16KB
• Ram Memory Size: 16KB
• Cpu Speed: 48MHz
• Oscillator Type: External Only
• No. Of Timers: 3
• Digital Ic Case Style: VFBGA
• Supply Voltage Range: 3V
• Controller Family/series: EZ-USB FX2LP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-08032 Rev. *K
10.17.4 Sequence Diagram of a Single and Burst Asynchronous Write
Figure 10-23 diagrams the timing relationship of the SLAVE
FIFO write in an asynchronous mode. The diagram shows a
single write followed by a burst write of 3 bytes and committing
the 4-byte-short packet using PKTEND.
FIFOADR
PKTEND
• At t = 0 the FIFO address is applied, insuring that it meets
• At t = 1 SLWR is asserted. SLWR must meet the minimum
• At t = 2, data must be present on the bus t
• At t = 3, deasserting SLWR will cause the data to be written
FLAGS
SLWR
the set-up time of t
asserted (SLCS may be tied low in some applications).
active pulse of t
of t
SLWR or before SLWR is asserted.
deasserting edge of SLWR.
from the data bus to the FIFO and then increments the FIFO
DATA
SLCS
WRpwh
. If the SLCS is used, it must be in asserted with
t=0
t
SFA
WRpwl
t =1
t
SFA
Figure 10-23. Slave FIFO Asynchronous Write Sequence and Timing Diagram
WRpwl
t=2
t
SFD
and minimum de-active pulse width
. If SLCS is used, it must also be
t=3
t
N
t
FDH
WRpwh
t
FAH
t
XFLG
T=0
SFD
t
SFA
T=1
before the
t
WRpwl
T=2
t
SFD
T=3
t
N+1
FDH
t
WRpwh
T=4
The same sequence of events are shown for a burst write and
is indicated by the timing marks of T = 0 through 5. Note: In
the burst write mode, once SLWR is deasserted, the data is
written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post incre-
mented.
In Figure 10-23 once the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet can be
committed to the host using the PKTEND. The external device
should be designed to not assert SLWR and the PKTEND
signal at the same time. It should be designed to assert the
PKTEND after SLWR is deasserted and met the minimum
deasserted pulse width. The FIFOADDR lines are to be held
constant during the PKTEND assertion.
t
WRpwl
T=5
pointer. The FIFO flag is also updated after t
deasserting edge of SLWR.
t
SFD
T=6
t
N+2
FDH
t
WRpwh
T=7
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
t
WRpwl
T=8
t
SFD
T=9
t
t
N+3
WRpwh
FDH
t
PEpwl
[20]
t
XFLG
t
PEpwh
t
Page 53 of 60
FAH
XFLG
from the