CY7C68014A-56BAXC Cypress Semiconductor Corp, CY7C68014A-56BAXC Datasheet - Page 47

• Manufacturer Part Number: CY7C68014A-56BAXC
• Description: IC MCU USB PERIPH HI SPD 56VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68014A-56BAXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• Core Size: 16bit
• No. Of I/o's: 24
• Program Memory Size: 16KB
• Ram Memory Size: 16KB
• Cpu Speed: 48MHz
• Oscillator Type: External Only
• No. Of Timers: 3
• Digital Ic Case Style: VFBGA
• Supply Voltage Range: 3V
• Controller Family/series: EZ-USB FX2LP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-08032 Rev. *K
auto mode and it is desired to send two packets back to back:
a full packet (full defined as the number of bytes in the FIFO
meeting the level set in AUTOINLEN register) committed
automatically followed by a short one byte/word packet
committed manually using the PKTEND pin. In this particular
scenario, user must make sure to assert PKTEND at least one
clock cycle after the rising edge that caused the last byte/word
to be clocked into the previous auto committed packet.
Figure 10-12 below shows this scenario. X is the value the
AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
10.12
Table 10-14. Slave FIFO Asynchronous Packet End Strobe Parameters
t
t
t
PKTEND
FIFOADR
IFCLK
SLWR
DATA
PEpwl
PWpwh
XFLG
Parameter
Slave FIFO Asynchronous Packet End Strobe
Figure 10-12. Slave FIFO Synchronous Write Sequence and Timing Diagram
Figure 10-13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
PKTEND Pulse Width LOW
PKTEND Pulse Width HIGH
PKTEND to FLAGS Output Propagation Delay
t
SFA
t
IFCLK
>= t
t
SFD
PKTEND
SWR
X-4
FLAGS
t
FDH
Description
t
SFD
X-3
t
FDH
t
SFD
X-2
t
PEpwl
t
XFLG
t
FDH
Figure 10-12 shows a scenario where two packets are being
committed. The first packet gets committed automatically
when the number of bytes in the FIFO reaches X (value set in
AUTOINLEN register) and the second one byte/word short
packet being committed manually using PKTEND. Note that
there is at least one IFCLK cycle timing between the assertion
of PKTEND and clocking of the last byte of the previous packet
(causing the packet to be committed automatically). Failing to
adhere to this timing, will result in the FX2 failing to send the
one byte/word short packet.
t
SFD
X-1
t
[23]
PEpwh
t
FDH
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Min.
50
50
t
SFD
X
t
FDH
At least one IFCLK cycle
t
SFD
Max.
115
1
[20]
[20]
>= t
t
FDH
WRH
Page 47 of 60
t
t
FAH
SPE
Unit
ns
ns
ns
t
PEH