CY7C68014A-56BAXC Cypress Semiconductor Corp, CY7C68014A-56BAXC Datasheet - Page 46

• Manufacturer Part Number: CY7C68014A-56BAXC
• Description: IC MCU USB PERIPH HI SPD 56VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68014A-56BAXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• Core Size: 16bit
• No. Of I/o's: 24
• Program Memory Size: 16KB
• Ram Memory Size: 16KB
• Cpu Speed: 48MHz
• Oscillator Type: External Only
• No. Of Timers: 3
• Digital Ic Case Style: VFBGA
• Supply Voltage Range: 3V
• Controller Family/series: EZ-USB FX2LP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-08032 Rev. *K
10.10
Table 10-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
10.11
Table 10-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
Table 10-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
There is no specific timing requirement that needs to be met
for asserting PKTEND pin with regards to asserting SLWR.
PKTEND can be asserted with the last data value clocked into
the FIFOs or thereafter. The only consideration is the set-up
time t
t
t
t
t
t
t
t
t
t
t
t
t
t
WRpwl
WRpwh
SFD
FDH
XFD
IFCLK
SPE
PEH
XFLG
IFCLK
SPE
PEH
XFLG
Parameter
Parameter
Parameter
SPE
Slave FIFO Asynchronous Write
Slave FIFO Synchronous Packet End Strobe
and the hold time t
SLWR Pulse LOW
SLWR Pulse HIGH
SLWR to FIFO DATA Set-up Time
FIFO DATA to SLWR Hold Time
SLWR to FLAGS Output Propagation Delay
IFCLK Period
PKTEND to Clock Set-up Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
IFCLK Period
PKTEND to Clock Set-up Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
Figure 10-11. Slave FIFO Synchronous Packet End Strobe Timing Diagram
SLWR/SLCS#
PEH
Figure 10-10. Slave FIFO Asynchronous Write Timing Diagram
PKTEND
FLAGS
DATA
FLAGS
SLWR
must be met.
IFCLK
Description
Description
Description
t
WRpwl
t
SFD
t
XFD
t
FDH
t
SPE
Although there are no specific timing requirements for the
PKTEND assertion, there is a specific corner case condition
that needs attention while using the PKTEND to commit a one
byte/word packet. There is an additional timing requirement
that need to be met when the FIFO is configured to operate in
t
WRpwh
t
t
PEH
XFLG
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
20.83
20.83
Min.
Min.
14.6
Min.
8.6
2.5
50
70
10
10
0
[23]
[20]
Max.
Max.
Max.
13.5
200
9.5
70
[20]
[21]
[21]
Page 46 of 60
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns