CY7C68014A-56BAXC Cypress Semiconductor Corp, CY7C68014A-56BAXC Datasheet - Page 10

• Manufacturer Part Number: CY7C68014A-56BAXC
• Description: IC MCU USB PERIPH HI SPD 56VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68014A-56BAXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• Core Size: 16bit
• No. Of I/o's: 24
• Program Memory Size: 16KB
• Ram Memory Size: 16KB
• Cpu Speed: 48MHz
• Oscillator Type: External Only
• No. Of Timers: 3
• Digital Ic Case Style: VFBGA
• Supply Voltage Range: 3V
• Controller Family/series: EZ-USB FX2LP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-08032 Rev. *K
EP2–1024
(column 8).
3.12.5
Table 3-6. Default Full-Speed Alternate Settings
3.12.6
Table 3-7. Default High-Speed Alternate Settings
Notes:
ep0
ep1out
ep1in
ep2
ep4
ep6
ep8
ep0
ep1out
ep1in
ep2
ep4
ep6
ep8
4.
5.
6.
“0” means “not implemented.”
“2×” means “double buffered.”
Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Alternate Setting
Alternate Setting
Default High-Speed Alternate Settings
Default Full-Speed Alternate Settings
EP0 IN&OUT
double
EP1 OUT
EP1 IN
buffered;
EP8
EP2
EP4
EP6
512
512
512
512
512
512
512
512
64
64
64
1
EP4
EP6
EP2
64
0
0
0
0
0
0
512
512
512
512
512
512
512
512
64
64
64
2
EP6–512
0
64
0
0
0
0
0
0
0
EP2
EP4
EP6
1024
1024
512
512
512
512
64
512 bulk
512 bulk
512 bulk out (2×)
512 bulk out (2×)
512 bulk in (2×)
512 bulk in (2×)
64
64
64
3
64
64 bulk
64 bulk
64 bulk out (2×)
64 bulk out (2×)
64 bulk in (2×)
64 bulk in (2×)
Figure 3-5. Endpoint Configuration
quad
[6]
[6]
EP2
EP8
EP6
512
512
512
512
512
512
512
64
64
64
512
4
[4, 5]
[4, 5]
buffered
1
1
EP2
EP6
512
512
512
512
512
512
512
512
64
64
64
5
EP2
EP6
1024
1024
512
512
512
512
64
64
64
6
64
64 int
64 int
512 int out (2×)
512 bulk out (2×)
512 int in (2×)
512 bulk in (2×)
64
64 int
64 int
64 int out (2×)
64 bulk out (2×)
64 int in (2×)
64 bulk in (2×)
EP2
EP8
EP6
1024
1024
512
512
512
64
64
64
512
7
EP2
1024
1024
EP6
512
512
512
512
64
64
64
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
8
2
2
EP2
EP6
1024
1024
1024
1024
64
64
64
9
EP2
EP6
EP8
512
512
512
512
512
512
512
512
64
64
64
10
64
64 int
64 int
512 iso out (2×)
512 bulk out (2×)
512 iso in (2×)
512 bulk in (2×)
64
64 int
64 int
64 iso out (2×)
64 bulk out (2×)
64 iso in (2×)
64 bulk in (2×)
EP2 EP2
1024
EP8
1024
1024
1024
64
64
64
512
512
11
1024
1024
1024
1024
12
64
64
64
3
3
Page 10 of 60