CY7C68014A-56BAXC Cypress Semiconductor Corp, CY7C68014A-56BAXC Datasheet - Page 52

• Manufacturer Part Number: CY7C68014A-56BAXC
• Description: IC MCU USB PERIPH HI SPD 56VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68014A-56BAXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• Core Size: 16bit
• No. Of I/o's: 24
• Program Memory Size: 16KB
• Ram Memory Size: 16KB
• Cpu Speed: 48MHz
• Oscillator Type: External Only
• No. Of Timers: 3
• Digital Ic Case Style: VFBGA
• Supply Voltage Range: 3V
• Controller Family/series: EZ-USB FX2LP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-08032 Rev. *K
10.17.3 Sequence Diagram of a Single and Burst Asynchronous Read
Figure 10-21 diagrams the timing relationship of the SLAVE
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
FLAGS
FIFOADR
FIFO POINTER
FIFO DATA BUS Not Driven
SLRD
SLCS
DATA
• At t = 0 the FIFO address is stable and the SLCS signal is
• At t = 1, SLOE is asserted. This results in the data bus being
• At t = 2, SLRD is asserted. The SLRD must meet the
SLOE
asserted.
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
minimum active pulse of t
pulse width of t
asserted before SLRD is asserted (i.e., the SLCS and SLRD
signals must both be asserted to start a valid read
condition.)
t=0
t=1
RDpwh
N
Driven
Figure 10-21. Slave FIFO Asynchronous Read Sequence and Timing Diagram
Data (X)
t
SFA
t
OEon
Figure 10-22. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLOE
. If SLCS is used then, SLCS must be
t=2
t
RDpwl
RDpwl
Driven: X
t
XFD
t=3
N
N
t=4
t
RDpwh
and minimum de-active
t
FAH
SLRD
t
OEoff
t
XFLG
N
N
SLRD
T=0
N+1
T=1
N
SLOE
t
t
SFA
OEon
N
T=2
Not Driven
t
N+1
RDpwl
t
XFD
T=3
SLOE
The same sequence of events is also shown for a burst read
marked with T = 0 through 5. Note: In burst read mode, during
SLOE is assertion, the data bus is in a driven state and outputs
the previous data. Once SLRD is asserted, the data from the
FIFO is driven on the data bus (SLOE must also be asserted)
and then the FIFO pointer is incremented.
• The data that will be driven, after asserting SLRD, is the
t
N+1
RDpwh
updated data from the FIFO. This data is valid after a propa-
gation delay of t
Figure 10-21, data N is the first valid data read from the
FIFO. For data to appear on the data bus during the read
cycle (i.e.,SLRD is asserted), SLOE MUST be in an
asserted state. SLRD and SLOE can also be tied together.
N+1
N
T=4
SLRD
t
RDpwl
t
XFD
N+1
T=5
N+1
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
SLRD
t
N+2
RDpwh
XFD
N+2
T=6
N+1
from the activating edge of SLRD. In
SLRD
t
RDpwl
t
XFD
N+3
N+2
N+2
T=7
t
t
RDpwh
FAH
SLRD
[20]
t
OEoff
t
XFLG
N+3
N+2
Page 52 of 60
SLOE
Not Driven
N+3