EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 992

• Manufacturer Part Number: EP4SGX290KF40C3N
• Description: IC STRATIX IV GX 290K 1517FBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX290KF40C3N

• Number Of Logic Elements/cells: 291200
• Number Of Labs/clbs: 11648
• Total Ram Bits: 17248
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2624

1–34
Table 1–9. MegaWizard Plug-In Manager Options (Clocking/Interface Screen) (Part 2 of 2)
Protocol Settings
Table 1–10. Protocol Settings
Stratix IV Device Handbook Volume 3
How should the transmitters
be clocked?
Create an 'rx_revbitorderwa'
input port to use receiver
enable bit reversal
Check a control box to use
the corresponding control
port.
Basic
Deterministic Latency
SDI
Serial RapidIO
ALTGX Setting
Protocols
1
This section describes the various screens available to set up the PCS blocks of the
Stratix IV transceiver.
Protocol Settings are not available for Basic (PMA Direct) functional mode.
Based on the protocol you select in the General screen of Parameter Settings, the
screens listed in
The following sections describe these screens and the available settings for each of
them.
Select one of the following available options:
■
■
This optional input port allows you to dynamically reverse the
bit order at the output of the receiver word aligner.
You can select various control and status signals depending
on what protocol(s) you intend to dynamically reconfigure
the transceiver channel to.
√ (Serial RapidIO/8B10B)
√ (Det. Latency/8B10B)
Share a single transmitter core clock between
transmitters
Use the respective channel transmitter core clocks
√ (Basic/8B10B)
√ (SDI/8B10B)
8B/10B
Table 1–10
become available.
Description
Protocol Settings Screens
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Word Aligner
√
√
√
√
Rate match/Byte order
February 2011 Altera Corporation
“Clocking/Interface
Options” section in the
Dynamic Reconfiguration in
Stratix IV Devices
“Word Aligner” section in
the
in Stratix IV Devices
chapter.
“FPGA Fabric-Transceiver
Channel Interface
Selection” section in the
Dynamic Reconfiguration in
Stratix IV Devices
Transceiver Architecture
Reference
—
—
√
√
Protocol Settings
chapter.
chapter.