EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 216
![IC STRATIX IV GX 290K 1517FBGA](/photos/6/73/67341/ds-1517fbga-1_3_sml.jpg)
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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6–44
Stratix IV Device Handbook Volume 1
Differential LVPECL
In Stratix IV devices, the LVPECL I/O standard is supported on input clock pins on
column and row I/O banks. LVPECL output operation is not supported in Stratix IV
devices. LVDS input buffers are used to support LVPECL input operation. AC
coupling is required when the LVPECL common-mode voltage of the output buffer is
higher than the LVPECL input common-mode voltage.
AC-coupled termination scheme. The 50-
external to the device.
Figure 6–32. LVPECL AC-Coupled Termination
Note to
(1) The LVPECL AC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
DC-coupled LVPECL is supported if the LVPECL output common mode voltage is
within the Stratix IV LVPECL input buffer specification
Figure 6–33. LVPECL DC-Coupled Termination
Note to
(1) The LVPECL DC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
Figure
Figure
LVPECL Output Buffer
LVPECL Output Buffer
6–32:
6–33:
Altera FPGA
Altera FPGA
0.1 μF
0.1 μF
Z
Z
Z
Z
O
O
O
O
= 50 Ω
= 50 Ω
= 50 Ω
= 50 Ω
Ω
(Note 1)
(Note 1)
resistors used at the receiver end are
V
ICM
100 Ω
Chapter 6: I/O Features in Stratix IV Devices
Figure 6–32
(Figure
50 Ω
50 Ω
Termination Schemes for I/O Standards
Stratix IV LVPECL
February 2011 Altera Corporation
Stratix IV LVPECL
Input Buffer
6–33).
Input Buffer
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