EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 1052
![IC STRATIX IV GX 290K 1517FBGA](/photos/6/73/67341/ds-1517fbga-1_3_sml.jpg)
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
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2–34
Stratix IV Device Handbook Volume 3
Create Reset Logic to Control the FPGA Fabric and Transceivers
The design requires independent control on each channel. Altera recommends
creating independent reset control logic for each channel.
In this design, channel 0 and channel 2 share the same CMU PLL (because they are
configured at the same data rate) and channel 1 uses the second CMU PLL. When you
create a Transmitter Only or Receiver and Transmitter instance, the ALTGX
MegaWizard Plug-In Manager provides a pll_powerdown signal to reset the
CMU PLL that provides clocks to the transmitter channel. In this design example,
because channels 0 and 2 share the same CMU PLL, drive the pll_powerdown port of
channel 0 and channel 2 in the ALTGX instance from the same logic.
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
February 2011 Altera Corporation
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