EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 839

• Manufacturer Part Number: EP4SGX290KF40C3N
• Description: IC STRATIX IV GX 290K 1517FBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX290KF40C3N

• Number Of Logic Elements/cells: 291200
• Number Of Labs/clbs: 11648
• Total Ram Bits: 17248
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2624

Chapter 4: Reset Control and Power Down in Stratix IV Devices
PMA Direct Drive Mode Reset Sequences
February 2011 Altera Corporation
As shown in
Direct) drive double-width configuration, non-bonded with CDR in automatic lock
mode, follow these reset steps:
1. After power up, assert pll_powerdown of each channel for a minimum period of
2. Keep the rx_analogreset signal of each channel asserted during this time period.
3. When the transmitter PLL locks, as indicated by the pll_locked signal going high
4. For the receiver operation, after de-assertion of the busy signal, wait for a
5. Wait for the rx_freqlocked signal from each channel to go high. The
6. In a Basic (PMA Direct) drive double-width configuration without bonding
t
After you de-assert the pll_powerdown signal on all channels, the transmitter PLL
of each channel starts locking to the transmitter input reference clock.
(marker 3), the transmitters are ready for accepting parallel data from the FPGA
fabric and subsequently transmitting serial data reliably.
minimum of two parallel clock cycles to de-assert the rx_analogreset signals of
each channel. After rx_analogreset is de-asserted, the receiver CDR of each
channel starts locking to the receiver input reference clock.
rx_freqlocked signal of each channel may go high at different times (indicated by
the slashed pattern at marker 6).
between channels, when the rx_freqlocked signals of all the channels have gone
high (marker 6), from that point onwards, wait for at least t
the receiver parallel clock to become stable. At this point, all the receivers are
ready for transferring valid parallel data into the FPGA fabric (until this time,
Altera recommends that the user logic that processes this data be under reset).
pll_powerdown
Figure
(the time between markers 1 and 2).
4–18, for the receiver and transmitter channel in Basic (PMA
Stratix IV Device Handbook Volume 2: Transceivers
LTD_Auto
(marker 7) for
4–33