EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 737

• Manufacturer Part Number: EP4SGX290KF40C3N
• Description: IC STRATIX IV GX 290K 1517FBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX290KF40C3N

• Number Of Logic Elements/cells: 291200
• Number Of Labs/clbs: 11648
• Total Ram Bits: 17248
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2624

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–34. FPGA Fabric-Receiver Interface Clocking for Non-Bonded Channel Configurations Without Rate Matcher
Note to
(1) The red lines represent rx_clkout[3], the blue lines represent rx_clkout[2], the green lines represent rx_clkout[1], and the brown lines
February 2011 Altera Corporation
(Note 1)
represent rx_clkout[0].
Figure
and Status
and Status
and Status
Channel 2
Channel 1
and Status
Channel 3
Channel 0
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
FPGA
Fabric
2–34:
rx_coreclk[2]
rx_coreclk[0]
rx_coreclk[1]
rx_coreclk[3]
Figure 2–34
channel configurations without rate matcher.
rx_clkout[1]
rx_clkout[0]
rx_clkout[2]
rx_clkout[3]
shows the FPGA fabric-Receiver interface clocking for non-bonded
Compensation
Compensation
Compensation
Compensation
rdclk
rdclk
rdclk
rdclk
RX Phase
RX Phase
RX Phase
RX Phase
FIFO
FIFO
FIFO
FIFO
wrclk
wrclk
wrclk
wrclk
/2
/2
/2
/2
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Parallel Recovered Clock
Parallel Recovered Clock
Parallel Recovered Clock
Parallel Recovered Clock
Stratix IV Device Handbook Volume 2: Transceivers
Channel 2
Channel 1
Channel 3
Channel 0
Receiver Channel PMA
Receiver Channel PMA
Receiver Channel PMA
Receiver Channel PMA
Receiver PMA
Receiver PMA
Receiver PMA
CDR
CDR
CDR
CDR
Input Reference Clock
rx_datain[2]
Input Reference Clock
rx_datain[3]
Input Reference Clock
rx_datain[1]
rx_datain[0]
2–65