EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 655
![IC STRATIX IV GX 290K 1517FBGA](/photos/6/73/67341/ds-1517fbga-1_3_sml.jpg)
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Port Lists
Table 1–73. Stratix IV GX and GT ALTGX Megafunction Ports: Transmitter Ports (Part 3 of 3)
February 2011 Altera Corporation
tx_invpolarity
Transmitter Physical Media Attachment
tx_dataout
fixedclk
Port Name
Output
Output
Input/
Input
Input
pulse width is two
signal. Minimum
Asynchronous
Clock Domain
parallel clock
Clock signal
cycles.
N/A
Transmitter polarity inversion control. This
feature is useful for correcting situations in
which the positive and negative signals of the
differential serial link are accidentally swapped
during board layout.
■
■
Transmitter serial data output port.
125-MHz clock for receiver detect and offset
cancellation in PCIe mode.
When asserted high in single-width
modes—the polarity of every bit of the 8-bit
or 10-bit input data to the serializer gets
inverted.
When asserted high in double-width
modes—the polarity of every bit of the
16-bit or 20-bit input data to the serializer
gets inverted.
Stratix IV Device Handbook Volume 2: Transceivers
Description
Channel
Channel
Channel
Scope
1–211
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