EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 806

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Using Enhanced Configuration Devices
Figure 12–15. Specifying Block Addresses for Application Configuration
12–28
Stratix Device Handbook, Volume 2
A sample memory map output file for the preceding example is shown
below. Note that the allocated memory for page 1 is between
0x00080000 and 0x001EFFFF, while the actual region used by the
current application configuration bitstream is between 0x001AB36C and
0x001EFFF7. The configuration data is top justified within the allocated
SOF data region.
Also note that the HEX data stored in the main data area uses absolute
addressing. If relative addressing were to be used, the main data contents
would be justified with the top (higher address locations) of the memory.
BOTTOM BOOT
OPTION BITS
PAGE 0
PAGE 1
TOP BOOT/MAIN
Block
0x00000000
0x00010000
0x00010040
0x001AB36C
0x001F0000
Start Address
0x000001FF
0x0001003F
0x00054CC8
0x001EFFF7
0x001F01FF
Altera Corporation
End Address
September 2004