EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 726

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Configuration Schemes
11–8
Stratix Device Handbook, Volume 2
PS Configuration with Configuration Devices
The configuration device scheme uses an Altera configuration device to
supply data to the Stratix or Stratix GX device in a serial bitstream (see
Figure
In the configuration device scheme, nCONFIG is usually tied to V
(when using EPC16, EPC8, EPC4, or EPC2 devices, nCONFIG may be
connected to nINIT_CONF). Upon device power-up, the target Stratix or
Stratix GX device senses the low-to-high transition on nCONFIG and
initiates configuration. The target device then drives the open-drain
CONF_DONE pin low, which in-turn drives the configuration device’s nCS
pin low. When exiting power-on reset (POR), both the target and
configuration device release the open-drain nSTATUS pin.
Before configuration begins, the configuration device goes through a POR
delay of up to 200 ms to allow the power supply to stabilize (power the
Stratix or Stratix GX device before or during the POR time of the
configuration device). This POR delay has a maximum of 200 ms for
EPC2 devices. For enhanced configuration devices, you can select
between 2 ms and 100 ms by connecting PORSEL pin to VCC or GND,
accordingly. During this time, the configuration device drives its OE pin
low. This low signal delays configuration because the OE pin is connected
to the target device’s nSTATUS pin. When the target and configuration
devices complete POR, they release nSTATUS, which is then pulled high
by a pull-up resistor.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. When all devices are ready, the
configuration device clocks data out serially to the target devices using an
internal oscillator.
After successful configuration, the Stratix FPGA starts initialization using
the 10-MHz internal oscillator as the reference clock. After initialization,
this internal oscillator is turned off. The CONF_DONE pin is released by the
target device and then pulled high by a pull-up resistor. When
initialization is complete, the FPGA enters user mode. The CONF_DONE
pin must have an external 10-k pull-up resistor in order for the device
to initialize.
If an error occurs during configuration, the target device drives its
nSTATUS pin low, resetting itself internally and resetting the
configuration device. If the Auto-Restart Configuration on Frame Error
option—available in the Quartus II Global Device Options dialog box
(Assign menu)—is turned on, the device reconfigures automatically if an
error occurs. To find this option, choose Compiler Settings (Processing
menu), then click on the Chips & Devices tab.
11–3).
Altera Corporation
July 2005
CC