EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 689

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
Architectural Element Names
The architectural element naming system within Stratix and Stratix GX
devices differs from the row-column coordinate system (for example,
LC1_A2, LAB_B1) used in previous Altera device families. Stratix and
Stratix GX devices uses a new naming system based on the X-Y
coordinate system, (X, Y). A number (N) designates the location within the
block where the logic resides, such as LEs within an LAB. Because the
Stratix and Stratix GX architectures are column-based, this naming
simplifies location assignments. Stratix and Stratix GX architectural
blocks include:
■
■
■
■
■
■
Elements within architectural blocks include:
■
■
■
■
■
■
LAB: logic array block
DSP: digital signal processing block
DSPOUT: adder/subtractor/accumulator or summation block of the
DSP block
M512: 512-bit memory block
M4K: 4-Kbit memory block
M-RAM: 512-Kbit memory block
LE: logic element
IOC: I/O element
PLL: phase-locked loop
DSPMULT: DSP block multiplier
SERDESTX: transmitter serializer/deserializer
SERDESRX: receiver serializer/deserializer
Transitioning APEX Designs to Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
10–5