EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 567

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
signa
signb
addnsub1
addnsub3
accum_sload0
accum_sload1
clock0
clock1
clock2
clock3
aclr0
aclr1
aclr2
aclr3
ena[3..0]
Table 6–4. Control Signals in DSP Block
Signal Name
1
6
3
7
2
7
3
4
5
6
1
4
5
7
Same rows as the
Clock Signals
Row
Each row block provides 18 bits of data to the multiplier (i.e., one of the
operands to the multiplier), which are routed through the 30 local
interconnects within each DSP row interface block. Any signal in the
device can be the source of the 18-bit multiplier data, by connecting to the
local row interconnect through any row or column.
Each control signal routes through one of the eight rows of the DSP block.
Table 6–4
routes.
Input/Output Data Interface Routing
The 30 local interconnects generate the 18 inputs to the row interface
blocks. The 21 outputs of the row interface block are the inputs to the DSP
row block (see
DSP block-wide signed and unsigned control signals for all multipliers.
The multiplier outputs are unsigned only if both
low.
Controls addition or subtraction of the two one-level adders. The
addnsub0
signal controls the bottom two one-level adders. A high indicates
addition; a low indicates subtraction.
Resets the feedback input to the accumulator. The signal
asynchronously clears the accumulator and allows new accumulation to
begin without losing any clock cycles. The
top two one-level adders, and the
two one-level adders. A low is for normal accumulation operations and
a high is for zeroing the accumulator.
DSP block-wide clock signals.
DSP block-wide clear signals.
DSP block-wide clock enable signals.
shows the 18 control signals and the row to which each one
Figure 6–7 on page
signal controls the top two one-level adders; the
DSP Blocks in Stratix & Stratix GX Devices
6–14).
Description
accum_sload1
Stratix Device Handbook, Volume 2
accum_sload0
signa
controls the bottom
and
addnsub1
controls the
signb
6–17
are