EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 623

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Matrix
Manipulation
Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Butterworth Filter Implementation Results
Table 7–16
filter as shown in
Butterworth Filter Design Example
Download the 4
example from the Design Examples section of the Altera web site at
www.altera.com.
DSP relies heavily on matrix manipulation. The key idea is to transform
the digital signals into a format that can then be manipulated
mathematically.
This section describes an example of matrix manipulation used in 2-D
convolution filter, and its implementation in a Stratix device.
Background on Matrix Manipulation
A matrix can represent all digital signals. Apart from the convenience of
compact notation, matrix representation also exploits the benefits of
linear algebra. As with one-dimensional, discrete sequences, this
advantage becomes more apparent when processing multi-dimensional
signals.
In image processing, matrix manipulation is important because it
requires analysis in the spatial domain. Smoothing, trend reduction, and
sharpening are examples of common image processing operations, which
are performed by convolution. This can also be viewed as a digital filter
operation with the matrix of filter coefficients forming a convolutional
kernel, or mask.
Part
Utilization
Performance
Latency
Table 7–16. 4
shows the results of implementing a 4
th
Order Butterworth Filter Implementation Results
th
Figure
Order Butterworth Filter (butterworth.zip) design
EP1S10F780C6
Lcell: 251/10570(2%)
DSP Block 9-bit elements: 16/48 (33%)
Memory bits: 0/920448 (0%)
80 MHz
4 clock cycles
7–25.
Stratix Device Handbook, Volume 2
th
order Butterworth
7–45