EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 692

IC STRATIX FPGA 20K LE 484-FBGA

EP1S20F484C6N

Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S20F484C6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
TriMatrix Memory
TriMatrix
Memory
10–8
Stratix Device Handbook, Volume 2
Figure 10–3. LE Numbering as Shown in the Quartus II Software
TriMatrix memory has three different sizes of memory blocks, each
optimized for a different purpose or application. M512 blocks consist of
512 bits plus parity (576 bits), M4K blocks consist of 4K bits plus parity
(4,608 bits), and M-RAM blocks consist of 512K bits plus parity
(589,824 bits). This new structure differs from APEX II and APEX 20K
devices, which feature uniformly sized embedded system blocks (ESBs)
either 4 Kbits (APEX II devices) or 2 Kbits (APEX 20K devices) large.
Stratix and Stratix GX TriMatrix memory blocks give you advanced
control of each memory block, with features such as byte enables, parity
bit storage, and shift-register mode, as well as mixed-port width support
and true dual-port mode operation.
Altera Corporation
July 2005

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