EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 626
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Matrix Manipulation
Figure 7–27. Using Free Boundary Condition for Edge Pixels
7–48
Stratix Device Handbook, Volume 2
Image boundary
0
0
0
3 x 3 kernel slides across image
x( x x m + 1, n )
x( x x
black pixels, that is pixels with value zero. This is similar to padding the
edges of the input image matrix with zeros and is referred to as the free
boundary condition. This is shown in
Convolution Implementation
This design example shows a 3
input image with gray pixel values ranging from 0-255 (8-bit). Data is fed
in serially starting from the top left pixel, moving horizontally on a row-
by-row basis. Next the data is stored in three separate RAM blocks in the
buffering stage. Each M512 memory block represents a line of the image,
and this is cycled through. For a 32
M4K memory blocks. For larger images (640
to M-RAM blocks or other buffering schemes. The control logic block
provides the RAM control signals to interleave the data across all three
0
x( x x m + 1, n + 1)
x( x x m , n + 1)
0
3 2-D FIR filter that takes in an 8
32 input image, the design needs
Figure
7–27.
480), this can be extended
Image boundary
Altera Corporation
Image
September 2004
8
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