EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 570

IC STRATIX FPGA 20K LE 484-FBGA

EP1S20F484C6N

Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S20F484C6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
Operational Modes
6–20
Stratix Device Handbook, Volume 2
summation block. You can use pipeline registers between the multiplier
stage and the summation block. The 36
signed and unsigned operation.
The 36-bit multiplier is useful when your application needs more than
18-bit precision, for example, for mantissa multiplication of precision
floating-point arithmetic applications.
36-bit multiplier supports
Altera Corporation
July 2005

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