EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 761

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 11–23. Embedded System Block Diagram
Notes to
(1)
(2)
Altera Corporation
July 2005
Connect the nCONFIG, MSEL2, MSEL1, and MSEL0 pins to support a non-JTAG configuration scheme. If your design
only uses JTAG configuration, connect the nCONFIG pin to V
Pull DATA0 and DCLK to either high or low.
Embedded System
Figure
Embedded
Processor
11–23:
to/from ByteBlasterMV
adr[19..0]
Control
d[7..0]
20
Both JTAG connection methods should include space for the
MasterBlaster or ByteBlasterMV header connection. The header is useful
during prototyping because it allows you to verify or modify the Stratix
or Stratix GX device’s contents. During production, you can remove the
header to save cost.
8
20
20
8
4
TDI
TMS
TCK
TDO
Control
d[3..0]
adr[19..0]
Control
d[7..0]
adr[19..0]
EPROM or
(Optional)
Interface
Memory
System
Logic
TDI
TMS
TCK
TDO
CC
and the MSEL2, MSEL1, and MSEL0 pins to ground.
Configuring Stratix & Stratix GX Devices
(2)
(2)
(1)
Stratix Device Handbook, Volume 2
TMS
TCK
TMS
TCK
TMS
TCK
DATA0
DCLK
nCONFIG
TMS
TCK
CONF_DONE
TDO
TDO
TDO
TDO
TDI
TDI
TDI
TDI
nCONFIG
nSTATUS
MSEL1
MSEL0
MSEL0
MSEL1
TRST
nCE
GND
V
CC
(1)
(1)
Cyclone FPGA
V
Any JTAG
Device
MAX
MAX 9000A,
MAX 7000S,
MAX 7000A,
MAX 7000AE,
or MAX 3000
Device
CC
Any Cyclone,
FLEX 10K,
FLEX 10KA,
FLEX10KE,
APEX 20K,
or APEX 20KE
Device
10 kΩ
®
9000,
V
CC
11–43
10 kΩ