EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 767
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Altera Corporation
July 2005
Jam Instructions
Each Jam statement begins with one of the instruction names listed in
Table
instructions, are reserved keywords that you cannot use as variable or
label identifiers in a Jam program.
Table 11–14
language. These keywords correspond to the state names specified in the
IEEE Std. 1149.1 JTAG specification.
Note to
(1)
BOOLEAN
CALL
CRC
DRSCAN
DRSTOP
EXIT
EXPORT
FOR
GOTO
IF
Test-Logic-Reset
Run-Test-Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-Scan
Table 11–13. Instruction Names
Table 11–14. Reserved Keywords (Part 1 of 2)
IEEE Std. 1149.1 JTAG State Names
This instruction name is an optional language extension.
11–13. The instruction names, including the names of the optional
Table
shows the state names that are reserved keywords in the Jam
11–13:
INTEGER
IRSCAN
IRSTOP
LET
NEXT
NOTE
POP
POSTDR
POSTIR
PREDR
Configuring Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
RESET
IDLE
DRSELECT
DRCAPTURE
DRSHIFT
DREXIT1
DRPAUSE
DREXIT2
DRUPDATE
IRSELECT
Jam Reserved State Names
PREIR
PRINT
PUSH
RETURN
STATE
WAIT
VECTOR
VMAP
–
–
(1)
(1)
11–49
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