EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 504

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Source-Synchronous Timing Budget
5–32
Stratix Device Handbook, Volume 2
t
f
t
C
HSCLK
RISE
Table 5–6. High-Speed Timing Specifications & Terminology (Part 1 of 2)
High-Speed Timing Specification
Table 5–5
18 differential channels. However, the MSB and LSB are increased with
the number of channels used in a system.
Timing Definition
The specifications used to define high-speed timing are described in
Table
Table 5–5. LVDS Bit Naming
Receiver Data Channel
5–6.
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Low-to-high transmission time.
shows the conventions for differential bit naming for
Number
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
MSB Position
Terminology
Internal 8-Bit Parallel Data
103
111
119
127
135
143
15
23
31
39
47
55
63
71
79
87
95
7
Altera Corporation
LSB Position
104
112
120
128
136
16
24
32
40
48
56
64
72
80
88
96
0
8
July 2005