EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 741

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
devices once they are released. When configuring multiple devices,
connect the nSTATUS pins together to ensure configuration only happens
when all devices release their OE or nSTATUS pins. The enhanced
configuration device then clocks data out in parallel to the Stratix or
Stratix GX device using a 66-MHz internal oscillator, or drives it to the
Stratix or Stratix GX device through the EXTCLK pin.
If there is an error during configuration, the Stratix or Stratix GX device
drives the nSTATUS pin low, resetting itself internally and resetting the
enhanced configuration device. The Quartus II software provides an
Auto-restart configuration after error option that automatically initiates
the reconfiguration whenever an error occurs. See the Software Settings
chapter in Volume 2 of the Configuration Handbook for information on how
to turn this option on or off.
If this option is turned off, you must set monitor nSTATUS to check for
errors. To initiate reconfiguration, pulse nCONFIG low. The external
system can pulse nCONFIG if it is under system control rather than tied to
V
to reprogram the Stratix or Stratix GX device on the fly.
When configuration is complete, the Stratix or Stratix GX device releases
the CONF_DONE pin, which is then pulled up by a resistor. This action
disables the EPC16, EPC8, or EPC4 enhanced configuration device as nCS
is driven high. Initialization, by default, uses an internal oscillator, which
runs at 10 MHz. After initialization, this internal oscillator is turned off.
When initialization is complete, the Stratix or Stratix GX device enters
user mode. The enhanced configuration device drives DCLK low before
and after configuration.
1
If, after sending out all of its data, the enhanced configuration device does
not detect CONF_DONE going high, it recognizes that the Stratix or
Stratix GX device has not configured successfully. The enhanced
configuration device pulses its OE pin low for a few microseconds,
driving the nSTATUS pin on the Stratix or Stratix GX device low. If the
Auto-restart configuration after error option is on, the Stratix or Stratix
GX device resets and then pulses its nSTATUS low. When nSTATUS
returns high, reconfiguration is restarted (see
page
CC
. Therefore, nCONFIG must be connected to nINIT_CONF if you want
11–25).
CONF_DONE goes high one byte early in parallel synchronous
(FPP) and asynchronous (PPA) modes using a microprocessor
with .rbf, .hex, and .ttf file formats. This does not apply to FPP
mode for enhanced configuration devices using .pof file format.
This also does not apply to serial modes.
Configuring Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
Figure 11–11 on
11–23