EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 546

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Software Support
Figure 5–47. SERDES Bypass LVDS Receiver with Logic Array as Deserializer
5–74
Stratix Device Handbook, Volume 2
data in
Serial
Clock
×4 clock0
÷2 clock1
PLL
Logic Array as Serializer/Deserializer Interface
The design can use the lpm_shift_reg megafunction instead of a
simple dual port memory block to serialize/deserialize data. The receiver
requires an extra flip-flop clocked by the slow clock to latch on to the
deserialized data. The transmitter requires a counter to generate the
enable signal for the shift register to indicate the times to load and
serialize the data.
LVDS receiver and
array performing the deserialization.
This scheme can also be used for APEX II and Mercury device flexible
LVDS solutions.
Input
DDR
data_h
data_l
Figures 5–47
clock
data
data
clock
×
8 LVDS transmitter, respectively, with the logic
Register
Register
data[1, 3, 5, 7]
data[0, 2, 4, 6]
Shift
Shift
and
5–48
data[7..0]
show the schematic of the
D
CLK
DFF[7..0]
Altera Corporation
Q
July 2005
Data to
logic array
rx_clk
×
8