EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 531

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
1,508-pin
FineLine
BGA
Table 5–14. EP1S80 Differential Channels (Part 2 of 2)
Package
The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second
row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center
PLL. For example, in the 780-pin FineLine BGA EP1S30 device, PLL 1 can drive a maximum of 18 transmitter
channels at 840 Mbps or a maximum of 35 transmitter channels at 840 Mbps. The Quartus II software may also
merge transmitter and receiver PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive
both the maximum numbers of receiver and transmitter channels.
Some of the channels accessible by the center fast PLL and the channels accessible by the corner fast PLL overlap.
Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and
4 with the number of channels accessible by PLLs 7, 8, 9, and 10. For more information on which channels overlap,
see the Fast PLL to High-Speed I/O Connections section in the relevant device pin table available on the web
(www.altera.com).
The corner fast PLLs in this device support a data rate of 840 Mbps for channels labeled “high” speed in the device
pin tables.
The numbers of channels listed include the transmitter clock output (tx_outclock) channel. You can use an extra
data channel if you need a DDR clock.
These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite
bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-bank
channels simultaneously if, for example, PLL_1 is clocking all receiver channels and PLL_2 is clocking all
transmitter channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank receiver channels or
two adjacent PLLs simultaneously clocking transmitter channels. Cross-bank allows for all receiver channels on one
side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the other
center PLL. Crossbank PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is
624 Mbps.
PLLs 7, 8, 9, and 10 are not available in this device.
The number in parentheses is the number of slow-speed channels, guaranteed to operate at up to 462 Mbps. These
channels are independent of the high-speed differential channels. For the location of these channels, see the Fast
PLL to High-Speed I/O Connections section in the relevant device pin table available on the web (www.altera.com).
See device pin-outs channels marked “high” speed are 840 Mbps and “low” speed channels are 462 MBps.
Tables 5–11
Transmitter
(4)
Receiver
Transmitter
/Receiver
through 5–14.
80 (72)
(7)
80 (56)
(7)
Channels
The Quartus II software may also merge transmitter and receiver PLLs
when a receiver block is driving a transmitter block if the Use Common
PLLs for Rx and Tx option is set for both modules. The Quartus II
software does not merge the PLLs in multiple transmitter-only or
multiple receiver-only modules fed by the same clock.
Total
Maximum
840
840
(Mbps)
Speed
840
840
(5)
(5)
,
,
(8)
(8)
High-Speed Differential I/O Interfaces in Stratix Devices
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
(10)
(20)
10
20
20
40
Center Fast PLLs
Note (1)
(10)
(20)
10
20
20
40
(10)
(20)
10
20
20
40
Stratix Device Handbook, Volume 2
(10)
(20)
10
20
20
40
(14)
(14)
20
(8)
20
(8)
10
10
Corner Fast PLLs
(14)
(14)
(8)
(8)
20
20
10
10
20 (8)
20 (8)
(14)
(14)
10
10
(2)
20 (8)
20 (8)
(14)
(14)
5–59
10
10