EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 736

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Configuration Schemes
11–18
Stratix Device Handbook, Volume 2
PS Configuration with a Microprocessor
In PS configuration with a microprocessor, a microprocessor transfers
data from a storage device to the target Stratix or Stratix GX device. To
initiate configuration in this scheme, the microprocessor must generate a
low-to-high transition on the nCONFIG pin and the target device must
release nSTATUS. The microprocessor or programming hardware then
places the configuration data one bit at a time on the DATA0 pin of the
Stratix or Stratix GX device. The least significant bit (LSB) of each data
byte must be presented first. Data is clocked continuously into the target
device until CONF_DONE goes high.
After all configuration data is sent to the Stratix or Stratix GX device, the
CONF_DONE pin goes high to show successful configuration and the start
of initialization. The CONF_DONE pin must have an external 10-k pull-
up resistor in order for the device to initialize. Initialization, by default,
uses an internal oscillator, which runs at 10 MHz. After initialization, this
internal oscillator is turned off. If you are using the clkusr option, after all
data is transferred clkusr must be clocked an additional 136 times for
the Stratix or Stratix GX device to initialize properly. Driving DCLK to the
device after configuration is complete does not affect device operation.
Handshaking signals are not used in PS configuration modes. Therefore,
the configuration clock speed must be below the specified frequency to
ensure correct configuration. No maximum DCLK period exists. You can
pause configuration by halting DCLK for an indefinite amount of time.
If the target device detects an error during configuration, it drives its
nSTATUS pin low to alert the microprocessor. The microprocessor can
then pulse nCONFIG low to restart the configuration process.
Alternatively, if the Auto-Restart Configuration on Frame Error option
is turned on in the Quartus II software, the target device releases
nSTATUS after a reset time-out period. After nSTATUS is released, the
microprocessor can reconfigure the target device without needing to
pulse nCONFIG low.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. If the microprocessor sends all
data and the initialization clock starts but CONF_DONE and INIT_DONE
have not gone high, it must reconfigure the target device. By default the
INIT_DONE output is disabled. You can enable the INIT_DONE output by
turning on Enable INIT_DONE output option in the Quartus II software.
If you do not turn on the Enable INIT_DONE output option in the
Quartus II software, you are advised to wait for the maximum value of
t
the device has been initialized properly and that it has entered user mode.
CD2UM
(see
Table
11–8) after the CONF_DONE signal goes high to ensure
Altera Corporation
July 2005