EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 506
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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f
frequency)
(LVDS, LVPECL,
HyperTransport
technology)
f
f
operation
(LVDS, LVPECL,
HyperTransport
technology)
f
frequency)
(PCML)
f
HSCLK
HSCLK
HSDR
HSCLK
HSCLK
Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 3)
Device
Symbol
(Clock
= f
(Clock
= f
HSDR
HSDR
/ W
/ W
W = 4 to 30
W = 2 (Serdes
bypass)
W = 2 (Serdes used)
W = 1 (Serdes
bypass)
W = 1 (Serdes used)
J = 10
J = 8
J = 7
J = 4
J = 2
J = 1 (LVDS and
LVPECL only)
W = 4 to 30 (Serdes
used)
W = 2 (Serdes
bypass)
W = 2 (Serdes used)
W = 1 (Serdes
bypass)
W = 1 (Serdes used)
Conditions
Tables 5–7
and
Min
150
100
300
300
300
300
300
100
100
150
100
300
10
50
10
50
5–8
-5 Speed Grade
show the high-speed I/O timing for Stratix devices
Typ
Max
210
231
420
462
717
840
840
840
840
462
462
100
200
200
250
400
Min
150
100
300
300
300
300
300
100
100
150
100
300
10
50
10
50
-6 Speed Grade
Typ
Notes
Max
210
231
420
462
717
840
840
840
840
462
462
100
200
200
250
400
(1),
Min
150
150
100
300
300
300
300
300
100
100
100
300
(2)
10
50
10
50
-7 Speed Grade
Typ
77.75
155.5
Max
156
231
312
462
624
640
640
640
640
640
640
150
200
311
Min
150
100
300
300
300
300
300
100
100
150
100
300
10
50
10
50
-8 Speed Grade
Typ
115.5
77.75
155.5
Max
231
231
462
462
462
462
462
462
462
462
150
200
311
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
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