EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 569
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
- Current page: 569 of 864
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Altera Corporation
July 2005
9- & 18-Bit Multipliers
You can configure each DSP block multiplier for 9 or 18 bits. A single DSP
block can support up to 8 individual 9-bit or smaller multipliers, or up to
4 individual multipliers with operand widths between 10- and 18-bits.
Figure 6–10
Figure 6–10. Simple Multiplier Mode
The multiplier operands can accept signed integers, unsigned integers, or
a combination. The signa and signb signals are dynamic and can be
registered in the DSP block. Additionally, you can register the multiplier
inputs and results independently. Pipelining the result, using the
pipeline registers in the block, increases the performance of the DSP
block.
36-Bit Multiplier
The 36-bit multiplier is a subset of the simple multiplier mode. It uses the
entire DSP block to implement one 36
multipliers are fed part of each input, as shown in
page
shiftoutb
6–21. The adder/output block adds the partial products using the
A
B
shows the simple multiplier mode.
shiftouta
ENA
ENA
D
D
CLRN
CLRN
signa
signb
Q
Q
DSP Blocks in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
36-bit multiplier. The four 18-bit
ENA
D
CLRN
Q
Figure 6–11 on
A
Adder Output Block
6–19
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