EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 323
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Figure 1–6. External Clock Outputs for Enhanced PLLs 11 & 12
Note to
(1)
Altera Corporation
July 2005
Counter
3.3-V GTL+
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-3 Class I
SSTL-3 Class II
AGP (1× and 2×)
CTT
Table 1–6. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2)
g 0
For PLL11, this pin is CLK13n; for PLL 12 this pin is CLK6n.
Figure
From Internal
I/O Standard
Logic or IOE
1–6:
Enhanced PLLs 11 and 12 support one single-ended output each (see
Figure
Therefore, to minimize jitter, do not place switching I/O pins next to this
output pin.
INCLK
1–6). These outputs do not have their own VCC and GND signals.
v
v
v
v
v
v
v
v
v
v
v
v
v
General-Purpose PLLs in Stratix & Stratix GX Devices
Input
FBIN
v
v
v
v
v
v
v
v
v
v
v
v
v
Stratix Device Handbook, Volume 2
PLLENABLE
or CLK6n, I/O, PLL12_OUT (1)
CLK13n, I/O, PLL11_OUT
EXTCLK
Output
v
v
v
v
v
v
v
v
v
v
v
v
v
1–13
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