LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 56

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

Revision 1.3 (02-23-10)
3.12.1
TX Buffer Format
TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the
TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32-
bit values that are used by the LAN89218 in the handling and processing of the associated Ethernet
packet data buffer. Buffer alignment, segmentation and other packet processing parameters are
included in the command structure. The following diagram illustrates the buffer format.
Figure 3.21, "TX Buffer
noted that not all of the data shown in this diagram is actually stored in the TX data FIFO. This must
be taken into account when calculating the actual TX data FIFO usage. Please refer to
"Calculating Actual TX Data FIFO Usage," on page 61
actual TX data FIFO usage.
Host Write
Order
2nd
3rd
Last
1st
Format", shows the TX Buffer as it is written into the LAN89218. It should be
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Figure 3.21 TX Buffer Format
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DATASHEET
Offset + Data DWORD0
Optional offset DWORD0
Optional offset DWORDn
Optional Pad DWORDn
Optional Pad DWORD0
TX Command 'B'
TX Command 'A'
Last Data & PAD
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for a detailed explanation on calculating the
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SMSC LAN89218
Section 3.12.5,
Datasheet